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PALCE22V10-15 Schematic ( PDF Datasheet ) - Cypress Semiconductor

Teilenummer PALCE22V10-15
Beschreibung Flash-erasable Reprogrammable CMOS PAL Device
Hersteller Cypress Semiconductor
Logo Cypress Semiconductor Logo 




Gesamt 13 Seiten
PALCE22V10-15 Datasheet, Funktion
PALCE22V10 is a replacement device for
PALC22V10, PALC22V10B, and PALC22V10D.
USE ULTRA37000TM FOR
ALL NEW DESIGNS
PALCE22V10
Flash-erasable Reprogrammable
CMOS PAL® Device
Features
Low power
— 90 mA max. commercial (10 ns)
— 130 mA max. commercial (5 ns)
• CMOS Flash EPROM technology for electrical erasabil-
ity and reprogrammability
• Variable product terms
— 2 ×(8 through 16) product terms
• User-programmable macrocell
— Output polarity control
— Individually selectable for registered or combina-
torial operation
• Up to 22 input terms and 10 outputs
Logic Block Diagram (PDIP/CDIP)
VSS I I I I
12 11
10
9
8
I
7
• DIP, LCC, and PLCC available
— 5 ns commercial version
4 ns tCO
3 ns tS
5 ns tPD
181-MHz state machine
— 10 ns military and industrial versions
7 ns tCO
6 ns tS
10 ns tPD
110-MHz state machine
— 15-ns commercial, industrial, and military versions
— 25-ns commercial, industrial, and military versions
• High reliability
— Proven Flash EPROM technology
— 100% programming and functional testing
II
I I I CP/I
6 5 4 3 21
PROGRAMMABLE
AND ARRAY
(132 X 44)
8 10 12 14 16 16 14 12 10
8
Reset
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Preset
13 14 15
I I/O9 I/O8
Pin Configuration
16 17
I/O 7
I/O6
LCC
Top View
18
I/O5
4 3 2 1 282726
I5
I6
25 I/O2
24 I/O3
I7
NC 8
23 I/O4
22 N/C
I9
I 10
21 I/O5
20 I/O6
I 11
19 I/O7
12131415161718
19 20 21 22
I/O4 I/O3 I/O2 I/O1
PLCC
Top View
4 3 2 1 2827 26
I5
25
I6
24
I7
23
NC 8
22
I9
21
I 10
20
I 11 121314 1516 1718 19
I/O2
I/O3
I/O4
N/C
I/O5
I/O6
I/O7
23 24
I/O0 VCC
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-03027 Rev. *B
Revised April 9, 2004






PALCE22V10-15 Datasheet, Funktion
USE ULTRA37000TM FOR
ALL NEW DESIGNS
PALCE22V10
Commercial Switching Characteristics PALCE22V10 (continued)[2, 7]
22V10-5
22V10-7 22V10-10
Parameter
Description
Min. Max. Min. Max. Min. Max.
tS1 Input or Feedback Set-Up Time 3 5 6
tS2
Synchronous Preset Set-Up
4
6
7
Time
tH
tP
tWH
tWL
fMAX1
fMAX2
fMAX3
tCF
Input Hold Time
000
External Clock Period (tCO + tS) 7
10 12
Clock Width HIGH[6]
2.5 3
3
Clock Width LOW[6]
2.5 3
3
External Maximum
143 100 76.9
Frequency (1/(tCO + tS))[11]
Data Path Maximum Frequency 200 166 142
(1/(tWH + tWL))[6, 12]
Internal Feedback Maximum
181
133
111
Frequency (1/(tCF + tS))[6,13]
Register Clock to
Feedback Input[6,14]
2.5 2.5
3
tAW Asynchronous Reset Width 8
tAR Asynchronous Reset
Recovery Time
4
8 10
56
tAP Asynchronous Reset to
Registered Output Delay
7.5 12 13
tSPR Synchronous Preset
Recovery Time
468
tPR Power-up Reset Time[6,15]
1
1
1
Military and Industrial Switching Characteristics PALCE22V10 [2, 7]
22V10-15
Min. Max.
10
10
0
20
6
6
55.5
83.3
68.9
4.5
15
10
20
10
1
22V10-25
Min. Max.
15
15
0
30
13
13
33.3
35.7
38.5
13
25
25
25
15
1
Unit
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
ns
ns
ns
ns
ns
µs
22V10-10
22V10-15
22V10-25
Parameter
Description
Min. Max. Min. Max. Min. Max.
Unit
tPD
Input to Output
Propagation Delay[8]
3 10 3 15 3 25 ns
tEA
Input to Output Enable Delay[9]
10
15
25 ns
tER
Input to Output Disable Delay[10]
10
15
25 ns
tCO
Clock to Output Delay[8]
2 7 2 8 2 15 ns
tS1
Input or Feedback Set-up Time
6
10 18
ns
tS2 Synchronous Preset Set-up Time 7
10 18
ns
tH Input Hold Time
0 0 0 ns
tP
External Clock Period (tCO + tS)
12
20
33
tWH Clock Width HIGH[6]
3
6 14
tWL Clock Width LOW[6]
3
6 14
ns
ns
ns
fMAX1
External Maximum Frequency
(1/(tCO + tS))[11]
76.9
50.0
30.3
MHz
fMAX2
Data Path Maximum Frequency
(1/(tWH + tWL))[6, 12 ]
142
83.3
35.7
MHz
Notes:
11. This specification indicates the guaranteed maximum frequency at which a state machine configuration with external feedback can operate.
12. This specification indicates the guaranteed maximum frequency at which the device can operate in data path mode.
13. This specification indicates the guaranteed maximum frequency at which a state machine configuration with internal only feedback can operate.
14. This parameter is calculated from the clock period at fMAX internal (1/fMAX3) as measured (see Note above) minus tS.
15. The registers in the PALCE22V10 have been designed with the capability to reset during system power-up. Following power-up, all registers will be reset to a
logic LOW state. The output state will depend on the polarity of the output buffer. This feature is useful in establishing state machine initialization. To insure proper
operation, the rise in VCC must be monotonic and the timing constraints depicted in Power-Up Reset Waveform must be satisfied.
Document #: 38-03027 Rev. *B
Page 6 of 13

6 Page









PALCE22V10-15 pdf, datenblatt
USE ULTRA37000TM FOR
ALL NEW DESIGNS
Package Diagrams (continued)
28-Square Leadless Chip Carrier L64
MIL-STD-1835 C-4
PALCE22V10
51-80051-**
Ultra37000 is a trademark of Cypress Semiconductor Corporation. PAL is a registered trademark of Advanced Micro Devices.
All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-03027 Rev. *B
Page 12 of 13
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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