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PDF ADuM3150 Data sheet ( Hoja de datos )
| Número de pieza | ADuM3150 | |
| Descripción | SPIsolator Digital Isolator | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Data Sheet
3.75 kV, 6-Channel, SPIsolator Digital
Isolator for SPI with Delay Clock
ADuM3150
FEATURES
Supports up to 40 MHz SPI clock speed in delay clock mode
Supports up to 17 MHz SPI clock speed in 4-wire mode
4 high speed, low propagation delay, SPI signal isolation
channels
2 data channels at 250 kbps
Delayed compensation clock line
20-lead SSOP with 5.1 mm creepage
High temperature operation: 125°C
High common-mode transient immunity: >25 kV/μs
Safety and regulatory approvals
UL recognition per UL 1577
3750 V rms for 1 minute
CSA Component Acceptance Notice 5A
VDE certificate of conformity
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
VIORM = 565 V peak
APPLICATIONS
Industrial programmable logic controllers (PLC)
Sensor isolation
GENERAL DESCRIPTION
The ADuM31501 is a 6-channel SPIsolator™ digital isolator
optimized for isolated serial peripheral interfaces (SPIs). Based
on the Analog Devices, Inc., iCoupler® chip scale transformer
technology, the low propagation delay in the CLK, MO/SI,
MI/SO, and SS SPI bus signals supports SPI clock rates of up to
17 MHz. These channels operate with 14 ns propagation delay
and 1 ns jitter to optimize timing for SPI.
The ADuM3150 isolator also provides two additional independent
low data rate isolation channels, one channel in each direction.
Data in the slow channels is sampled and serialized for a 250 kbps
data rate with 2.5 μs of jitter.
The ADuM3150 supports a delay clock output on the master
side of the device. This output can be used with an additional
clocked port on the master to support 40 MHz clock performance.
See the Delay Clock section for more information.
FUNCTIONAL BLOCK DIAGRAM
VDD1 1
GND1 2
MCLK 3
MO 4
MI 5
MSS 6
ADuM3150
ENCODE
ENCODE
DECODE
ENCODE
VIA 7
VOB 8
CONTROL
BLOCK
DCLK 9
GND1 10
CLK
DELAY
DECODE
DECODE
ENCODE
DECODE
CONTROL
BLOCK
20 VDD2
19 GND2
18 SCLK
17 SI
16 SO
15 SSS
14 VOA
13 VIB
12 NIC
11 GND2
Figure 1.
Table 1. Related Products
Product
Description
ADuM3151/ADuM3152/
ADuM3153
3.75 kV, multichannel SPI isolator
ADuM3154
3.75 kV, multiple slave SPI isolator
ADuM4150
5 kV, high speed, clock delayed
SPIsolator
ADuM4151/ADuM4152/
ADuM4153
5 kV, multichannel SPI isolator
ADuM4154
5 kV, multiple slave SPI isolator
1 Protected by U.S. Patents 5,952,849; 6,873,065; 6,262,600; and 7,075,329. Other patents are pending.
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2014–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
ADuM3150
Data Sheet
Table 3. For All Grades1, 2, 3
Parameter
SUPPLY CURRENT
1 MHz, A Grade and B Grade
17 MHz, B Grade
DC SPECIFICATIONS
MCLK, MSS, MO, SO, VIA, VIB
Input Threshold
Logic High
Logic Low
Input Hysteresis
Input Current per Channel
SCLK, SSS, MI, SI, VOA, VOB, DCLK
Output Voltages
Logic High
Logic Low
VDD1, VDD2 Undervoltage Lockout
Supply Current for High Speed Channel
Dynamic Input
Dynamic Output
Supply Current for All Low Speed Channels
Quiescent Side 1 Current
Quiescent Side 2 Current
AC SPECIFICATIONS
Output Rise/Fall Time
Common-Mode Transient Immunity4
Symbol Min
IDD1
IDD2
IDD1
IDD2
Typ Max
5 8.5
6.5 11
15 23
13.5 21
Unit
mA
mA
mA
mA
Test Conditions/Comments
CL = 0 pF, DRFAST = 1 MHz,
DRSLOW = 0 MHz
CL = 0 pF, DRFAST = 1 MHz,
DRSLOW = 0 MHz
CL = 0 pF, DRFAST = 17 MHz,
DRSLOW = 0 MHz
CL = 0 pF, DRFAST = 17 MHz,
DRSLOW = 0 MHz
VIH
VIL
VIHYST
II
0.7 × VDDx
−1
500
+0.01
0.3 × VDDx
+1
V
V
mV
µA
0 V ≤ VINPUT ≤ VDDx
VOH
VOL
UVLO
IDDI(D)
IDDO(D)
IDD1(Q)
IDD2(Q)
tR/tF
|CM|
VDDx − 0.1
VDDx − 0.4
5.0
4.8
0.0
0.2
2.6
0.1
0.4
0.080
0.046
4.4
6.1
2.5
25 35
V IOUTPUT = −20 µA, VINPUT = VIH
V IOUTPUT = −4 mA, VINPUT = VIH
V IOUTPUT = 20 µA, VINPUT = VIL
V IOUTPUT = 4 mA, VINPUT = VIL
V
mA/Mbps
mA/Mbps
mA
mA
ns
kV/µs
10% to 90%
VINPUT = VDDx, VCM = 1000 V
Transient magnitude = 800 V
1 VDDx = VDD1 or VDD2.
2 VINPUT is the input voltage of any of the MCLK, MSS, MO, SO, VIA, or VIB pins.
3 IOUTPUT is the output current of any of the SCLK, DCLK, SSS, MI, SI, VOA, or VOB pins.
4 |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining output voltages within the VOH and VOL limits. The common-mode
voltage slew rates apply to both rising and falling common-mode voltage edges.
Rev. B | Page 4 of 21
5 Page 
ADuM3150
Data Sheet
Table 9. For All Grades1, 2, 3
Parameter
SUPPLY CURRENT
1 MHz, A Grade and B Grade
17 MHz, B Grade
DC SPECIFICATIONS
MCLK, MSS, MO, SO, VIA, VIB
Input Threshold
Logic High
Logic Low
Input Hysteresis
Input Current per Channel
SCLK, SSS, MI, SI, VOA, VOB, DCLK
Output Voltages
Logic High
Logic Low
VDD1, VDD2 Undervoltage Lockout
Supply Current for All Low Speed Channels
Quiescent Side 1 Current
Quiescent Side 2 Current
AC SPECIFICATIONS
Output Rise/Fall Time
Common-Mode Transient Immunity4
Symbol Min
IDD1
IDD2
IDD1
IDD2
Typ Max
3.5 6
6.8 11
12.5 20
14 21
Unit
mA
mA
mA
mA
VIH
VIL
VIHYST
II
0.7 × VDDx
−1
500
+0.01
0.3 × VDDx
+1
V
V
mV
µA
VOH
VOL
UVLO
IDD1(Q)
IDD2(Q)
tR/tF
|CM|
VDDx − 0.1
VDDx − 0.4
5.0
4.8
0.0
0.2
2.6
2.9
6.1
2.5
25 35
0.1
0.4
V
V
V
V
V
mA
mA
ns
kV/µs
Test Conditions/Comments
CL = 0 pF, DRFAST = 1 MHz,
DRSLOW = 0 MHz
CL = 0 pF, DRFAST = 1 MHz,
DRSLOW = 0 MHz
CL = 0 pF, DRFAST = 17 MHz,
DRSLOW = 0 MHz
CL = 0 pF, DRFAST = 17 MHz,
DRSLOW = 0 MHz
0 V ≤ VINPUT ≤ VDDx
IOUTPUT = −20 µA, VINPUT = VIH
IOUTPUT = −4 mA, VINPUT = VIH
IOUTPUT = 20 µA, VINPUT = VIL
IOUTPUT = 4 mA, VINPUT = VIL
10% to 90%
VINPUT = VDDx, VCM = 1000 V
Transient magnitude = 800 V
1 VDDx = VDD1 or VDD2.
2 VINPUT is the input voltage of any of the MCLK, MSS, MO, SO, VIA, or VIB pins.
3 IOUTPUT is the output current of any of the SCLK, DCLK, SSS, MI, SI, VOA, or VOB pins.
4 |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining output voltages within the VOH and VOL limits. The common-mode
voltage slew rates apply to both rising and falling common-mode voltage edges.
Rev. B | Page 10 of 21
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet ADuM3150.PDF ] | |
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