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PDF ADAU1451 Data sheet ( Hoja de datos )
| Número de pieza | ADAU1451 | |
| Descripción | SigmaDSP Digital Audio Processor | |
| Fabricantes | Analog Devices | |
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Data Sheet
SigmaDSP Digital Audio Processor
ADAU1452/ADAU1451/ADAU1450
FEATURES
Integer PLL and flexible clock generators
Qualified for automotive applications
Fully programmable audio DSP for enhanced sound processing
Features SigmaStudio, a proprietary graphical programming
tool for the development of custom signal flows
Up to 294.912 MHz, 32-bit SigmaDSP core at 1.2 V
Up to 6144 SIMD instructions per sample at 48 kHz
Up to 40 kWords of parameter/data RAM
Up to 800 ms digital audio delay pool at 48 kHz
Audio I/O and routing
4 serial input ports, 4 serial output ports
Integrated die temperature sensor
I2C and SPI control interfaces (both slave and master)
Standalone operation
Self boot from serial EEPROM
6-channel, 10-bit SAR auxiliary control ADC
14 multipurpose pins for digital controls and outputs
On-chip regulator for generating 1.2 V from 3.3 V supply
72-lead, 10 mm × 10 mm LFCSP package with 5.3 mm
exposed pad
Temperature range: −40°C to +105°C
48-channel, 32-bit digital I/O up to a sample rate of 192 kHz
Flexible configuration for TDM, I2S, left and right justified
formats, and PCM
Up to 8 stereo ASRCs from 1:8 up to 7.75:1 ratio and
139 dB DNR
Stereo S/PDIF input and output (not on the ADAU1450)
Four PDM microphone input channels
Multichannel, byte addressable TDM serial ports
APPLICATIONS
Automotive audio processing
Head units
Navigation systems
Rear seat entertainment systems
DSP amplifiers (sound system amplifiers)
Commercial and professional audio processing
Clock oscillator for generating master clock from crystal
FUNCTIONAL BLOCK DIAGRAM—ADAU1452/ADAU1451
VDRIVE
THD_P
THD_M
SPI/I2C* SPI/I2C*
ADAU1452/
ADAU1451
PLLFILT
REGULATOR
TEMPERATURE
SENSOR
I2C/SPI
SLAVE
I2C/SPI
MASTER
GPIO/
AUX ADC
CLOCK
PLL OSCILLATOR
CLKOUT
SPDIFIN
SDATA_IN3 TO SDATA_IN0
(48-CHANNEL
DIGITAL AUDIO
INPUTS)
BCLK_IN3 TO BCLK_IN0/
LRCLK_IN3 TO LRCLK_IN0
(INPUT CLOCK PAIRS)
INPUT AUDIO
ROUTING MATRIX
S/PDIF
RECEIVER
294.912MHz 2
PROGRAMMABLE AUDIO
PROCESSING CORE
RAM, ROM, WATCHDOG,
MEMORY PARITY CHECK
OUTPUT AUDIO
ROUTING MATRIX
S/PDIF
TRANSMITTER
SERIAL DATA
INPUT PORTS
(×4)
DIGITAL
MIC INPUT
8 × 2-CHANNEL
ASYNCHRONOUS
SAMPLE RATE
CONVERTERS
SERIAL DATA
OUTPUT PORTS
(×4)
INPUT
CLOCK
DOMAINS
(×4)
DEJITTER AND
CLOCK GENERATOR
OUTPUT
CLOCK
DOMAINS
(×4)
SPDIFOUT
SDATA_OUT3 TO SDATA_OUT0
(48-CHANNEL
DIGITAL AUDIO
OUTPUTS)
BCLK_OUT3 TO BCLK_OUT0
LRCLK_OUT3 TO LRCLK_OUT0
(OUTPUT CLOCK PAIRS)
*SPI/I2C INCLUDES THE FOLLOWING PIN FUNCTIONS: SS_M, MOSI_M, SCL_M, SCLK_M, SDA_M, MISO_M, MISO, SDA,
SCLK, SCL, MOSI, ADDR1, SS, AND ADDR0 PINS.
Figure 1.
Rev. B
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rights of third parties that may result from its use. Specifications subject to change without notice. No
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Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2013–2014 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
Data Sheet
FUNCTIONAL BLOCK DIAGRAM—ADAU1450
ADAU1452/ADAU1451/ADAU1450
VDRIVE
THD_P
THD_M
SPI/I2C* SPI/I2C*
ADAU1450
REGULATOR
TEMPERATURE
SENSOR
I2C/SPI
SLAVE
I2C/SPI
MASTER
GPIO/
AUX ADC
PLLFILT
CLOCK
PLL OSCILLATOR
CLKOUT
SDATA_IN3 TO SDATA_IN0
(48-CHANNEL
DIGITAL AUDIO
INPUTS)
BCLK_IN3 TO BCLK_IN0/
LRCLK_IN3 TO LRCLK_IN0
(INPUT CLOCK PAIRS)
INPUT AUDIO
ROUTING MATRIX
147.456MHz
PROGRAMMABLE AUDIO
PROCESSING CORE
RAM, ROM, WATCHDOG,
MEMORY PARITY CHECK
OUTPUT AUDIO
ROUTING MATRIX
SERIAL DATA
INPUT PORTS
(×4)
DIGITAL
MIC INPUT
INPUT
CLOCK
DOMAINS
(×4)
SERIAL DATA
OUTPUT PORTS
(×4)
DEJITTER AND
CLOCK GENERATOR
OUTPUT
CLOCK
DOMAINS
(×4)
SDATA_OUT3 TO SDATA_OUT0
(48-CHANNEL
DIGITAL AUDIO
OUTPUTS)
BCLK_OUT3 TO BCLK_OUT0
LRCLK_OUT3 TO LRCLK_OUT0
(OUTPUT CLOCK PAIRS)
*SPI/I2C INCLUDES THE FOLLOWING PIN FUNCTIONS: SS_M, MOSI_M, SCL_M, SCLK_M, SDA_M, MISO_M, MISO, SDA,
SCLK, SCL, MOSI, ADDR1, SS, AND ADDR0 PINS.
Figure 2.
Rev. B | Page 5 of 180
5 Page 
Data Sheet
ADAU1452/ADAU1451/ADAU1450
Multipurpose Pins
TA = −40°C to +105°C, DVDD = 1.2 V ± 5%, IOVDD = 1.8 V − 10% to 3.3 V + 10%.
Table 9.
Parameter
MULTIPURPOSE PINS (MPx)
fMP1
Min
tMPIL1
10 × tCORE
Max Unit
24.576
MHz
6144 × tCORE sec
Description
MPx maximum switching rate when pin is configured as a general-purpose
input or general-purpose output
MPx pin input latency until high/low value is read by core; the duration in the
Max column is equal to the period of one audio sample when the DSP is
processing 6144 instructions per sample
1 Guaranteed by design.
S/PDIF Transmitter
TA = −40°C to +105°C, DVDD = 1.2 V ± 5%, IOVDD = 1.8 V − 10% to 3.3 V + 10%.
Table 10.
Parameter
S/PDIF Transmitter
Audio Sample Rate
Min Max
18 96
Unit Description
kHz Audio sample rate of data output from S/PDIF transmitter
S/PDIF Receiver
TA = −40°C to +105°C, DVDD = 1.2 V ± 5%, IOVDD = 1.8 V − 10% to 3.3 V + 10%.
Table 11.
Parameter
S/PDIF Receiver
Audio Sample Rate
Min Max
18 96
Unit Description
kHz Audio sample rate of data input to S/PDIF receiver
Rev. B | Page 11 of 180
11 Page | ||
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