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CAT28C513 Schematic ( PDF Datasheet ) - ON Semiconductor

Teilenummer CAT28C513
Beschreibung 512K-Bit CMOS PARALLEL EEPROM
Hersteller ON Semiconductor
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Gesamt 12 Seiten
CAT28C513 Datasheet, Funktion
CAT28C512/513
512K-Bit CMOS PARALLEL EEPROM
FEATURES
s Fast Read Access Times: 120/150 ns
s Low Power CMOS Dissipation:
–Active: 50 mA Max.
–Standby: 200 µA Max.
s Simple Write Operation:
–On-Chip Address and Data Latches
–Self-Timed Write Cycle with Auto-Clear
s Fast Write Cycle Time:
–5ms Max
s CMOS and TTL Compatible I/O
DESCRIPTION
The CAT28C512/513 is a fast,low power, 5V-only CMOS
parallel EEPROM organized as 64K x 8-bits. It requires
a simple interface for in-system programming. On-chip
address and data latches, self-timed write cycle with
auto-clear and VCC power up/down write protection
eliminate additional timing and protection hardware.
DATA Polling and Toggle status bits signal the start and
end of the self-timed write cycle. Additionally, the
CAT28C512/513 features hardware and software write
protection.
BLOCK DIAGRAM
s Automatic Page Write Operation:
–1 to 128 Bytes in 5ms
–Page Load Timer
s End of Write Detection:
–Toggle Bit
DATA Polling
s Hardware and Software Write Protection
s 100,000 Program/Erase Cycles
s 100 Year Data Retention
s Commercial, Industrial and Automotive
Temperature Ranges
The CAT28C512/513 is manufactured using Catalyst’s
advanced CMOS floating gate technology. It is designed
to endure 100,000 program/erase cycles and has a data
retention of 100 years. The device is available in JEDEC
approved 32-pin DIP, PLCC and TSOP packages.
A7A15
VCC
CE
OE
WE
A0A6
ADDR. BUFFER
& LATCHES
INADVERTENT
WRITE
PROTECTION
CONTROL
TIMER
ADDR. BUFFER
& LATCHES
ROW
DECODER
HIGH VOLTAGE
GENERATOR
DATA POLLING
AND
TOGGLE BIT
COLUMN
DECODER
65,536 x 8
EEPROM
ARRAY
128 BYTE PAGE
REGISTER
I/O BUFFERS
I/O0I/O7
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
1
Doc. No. MD-1007, Rev. I






CAT28C513 Datasheet, Funktion
CAT28C512/513
DEVICE OPERATION
Read
Data stored in the CAT28C512/513 is transferred to the
data bus when WE is held high, and both OE and CE
are held low. The data bus is set to a high impedance
state when either CE or OE goes high. This 2-line control
architecture can be used to eliminate bus contention in
a system environment.
Byte Write
A write cycle is executed when both CE and WE are low,
and OE is high. Write cycles can be initiated using either
WE or CE, with the address input being latched on the
falling edge of WE or CE, whichever occurs last. Data,
conversely, is latched on the rising edge of WE or CE,
whichever occurs first. Once initiated, a byte write cycle
automatically erases the addressed byte and the new
data is written within 5 ms.
Figure 3. Read Cycle
ADDRESS
CE
OE
WE
DATA OUT
tRC
tCE
tOE
VIH
tLZ
HIGH-Z
tOLZ
tOH
DATA VALID
tAA
tOHZ
tHZ
DATA VALID
Figure 4. Byte Write Cycle [WE Controlled]
ADDRESS
CE
tAS tAH
tCS
tCH
OE
WE
DATA OUT
DATA IN
Doc. No. MD-1007, Rev. I
tOES
tWP
HIGH-Z
tOEH
tBLC
DATA VALID
tDS
tDH
6
tWC
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice

6 Page









CAT28C513 pdf, datenblatt
CAT28C512/513
REVISION HISTORY
Date
19-Apr-04
17-Nov-04
15-Oct-08
20-Nov-08
28-Jul-09
Revision Description
Delete data sheet designation
Update Block Diagram
E Update Ordering Information
Add Revision History
Update Rev Number
F Delete T14 and H14 package codes
G Eliminate PDIP SnPb package
H Change logo and fine print to ON Semiconductor
I
Update Example of Ordering Information
Update Ordering Information table
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Doc. No. MD-1007, Rev. I
12
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice

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