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ADP3650 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADP3650
Beschreibung 12V MOSFET Driver
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 12 Seiten
ADP3650 Datasheet, Funktion
FEATURES
All-in-one synchronous buck driver
Bootstrapped high-side drive
One PWM signal generates both drives
Anti-crossconduction protection circuitry
OD for disabling the driver outputs
APPLICATIONS
Telecom and datacom networking
Industrial and medical systems
Point of load conversion: memory, DSP, FPGA, ASIC
Dual, Bootstrapped, 12 V MOSFET
Driver with Output Disable
ADP3650
GENERAL DESCRIPTION
The ADP3650 is a dual, high voltage MOSFET driver optimized
for driving two N-channel MOSFETs, the two switches in a
nonisolated synchronous buck power converter. Each driver is
capable of driving a 3000 pF load with a 45 ns propagation delay
and a 25 ns transition time. One of the drivers can be boot-
strapped and is designed to handle the high voltage slew rate
associated with floating high-side gate drivers. The ADP3650
includes overlapping drive protection to prevent shoot-through
current in the external MOSFETs.
The OD pin shuts off both the high-side and the low-side
MOSFETs to prevent rapid output capacitor discharge during
system shutdown.
The ADP3650 is specified over the temperature range of −40°C
to +85°C and is available in 8-lead SOIC_N and 8-lead LFCSP_VD
packages.
FUNCTIONAL BLOCK DIAGRAM
12V
ADP3650
IN 2
VCC
4
DELAY
LATCH
R1
R2 Q
S
OD 3
CMP
1V
DELAY
CMP
VCC
6
CONTROL
LOGIC
Figure 1.
D1
BST
1
CBST1
DRVH
8
CBST2
RG
Q1
SW
7
RBST
TO
INDUCTOR
DRVL
5
PGND
6
Q2
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2008–2010 Analog Devices, Inc. All rights reserved.






ADP3650 Datasheet, Funktion
ADP3650
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
BST 1
IN 2
OD 3
VCC 4
ADP3650
TOP VIEW
(Not to Scale)
8 DRVH
7 SW
6 PGND
5 DRVL
Figure 4. 8-Lead SOIC_N Pin Configuration
BST 1
IN 2
OD 3
VCC 4
PIN 1
INDICATOR
ADP3650
TOP VIEW
(Not to Scale)
8 DRVH
7 SW
6 PGND
5 DRVL
NOTES
1. IT IS RECOMMENDED THAT THE
EXPOSED PAD AND THE PGND PIN
BE CONNECTED ON THE PCB.
Figure 5. 8-Lead LFCSP_VD Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1 BST
Upper MOSFET Floating Bootstrap Supply. A capacitor connected between the BST and SW pins holds this
bootstrapped voltage for the high-side MOSFET while it is switching.
2 IN
Logic Level PWM Input. This pin has primary control of the drive outputs. In normal operation, pulling this pin
low turns on the low-side driver; pulling it high turns on the high-side driver.
3 OD
Output Disable. When low, this pin disables normal operation, forcing DRVH and DRVL low.
4 VCC
Input Supply. This pin should be bypassed to PGND with an ~1 µF ceramic capacitor.
5 DRVL
Synchronous Rectifier Drive. Output drive for the lower (synchronous rectifier) MOSFET.
6 PGND
Power Ground. This pin should be closely connected to the source of the lower MOSFET. This pin is not internally
connected to the exposed pad on the LFCSP. It is recommended that this pin and the exposed pad be
connected on the PCB.
7 SW
Switch Node Connection. This pin is connected to the buck switching node, close to the upper MOSFET source.
It is the floating return for the upper MOSFET drive signal. It is also used to monitor the switched voltage to
prevent the lower MOSFET from turning on until the voltage is below ~1 V.
8 DRVH
Buck Drive. Output drive for the upper (buck) MOSFET.
EP Exposed pad For the LFCSP, the exposed pad and the PGND pin should be connected on the PCB. For more information
about exposed pad packages, see the AN-772 Application Note at www.analog.com.
Rev. A | Page 6 of 12

6 Page









ADP3650 pdf, datenblatt
ADP3650
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
8
1
5
6.20 (0.2441)
4 5.80 (0.2284)
0.25 (0.0098)
0.10 (0.0040)
1.27 (0.0500)
BSC
1.75 (0.0688)
1.35 (0.0532)
COPLANARITY
0.10 SEATING
PLANE
0.51 (0.0201)
0.31 (0.0122)
0.50 (0.0196)
0.25 (0.0099)
45°
1.27 (0.0500)
0.25 (0.0098) 0.40 (0.0157)
0.17 (0.0067)
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 16. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
PIN 1
INDICATOR
3.25
3.00 SQ
2.75
TOP
VIEW
0.60 MAX
0.60 MAX
0.50
BSC
2.95
2.75 SQ
2.55
58
EXPOSED
PAD
(BOTTOM VIEW)
1.60
1.45
1.30
12° MAX
0.90 MAX
0.85 NOM
SEATING
PLANE
0.70 MAX
0.65 TYP
0.30
0.23
0.18
0.50
0.40
0.30
0.05 MAX
0.01 NOM
0.20 REF
41
PIN 1
1.89 INDICATOR
1.74
1.59
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
Figure 17. 8-Lead Lead Frame Chip Scale Package [LFCSP_VD]
3 mm x 3 mm Body, Very Thin, Dual Lead
(CP-8-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
ADP3650JRZ
ADP3650JRZ-RL
ADP3650JCPZ-RL
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
1 Z = RoHS Compliant Part.
Package Description
8-Lead Standard Small Outline Package (SOIC_N)
8-Lead Standard Small Outline Package (SOIC_N)
8-Lead Lead Frame Chip Scale Package (LFCSP_VD)
Package
Option
R-8
R-8
CP-8-2
Ordering
Quantity
98
2,500
5,000
Branding
L91
©2008–2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07826-0-7/10(A)
Rev. A | Page 12 of 12

12 Page





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