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PDF A7B Data sheet ( Hoja de datos )
| Número de pieza | A7B | |
| Descripción | Single-cell Li-ion / Li-polymer Battery Protection IC | |
| Fabricantes | AnaSem | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de A7B (archivo pdf) en la parte inferior de esta página. Total 23 Páginas | ||
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AnaSem
Analog Semiconductor IC
A7B Series
Single-cell Li-ion / Li-polymer
Battery Protection IC
Rev. E09-06
AnaSem Inc.
.......... Future of the analog world
1 page  
Rev. E09-06
Single-cell Li-ion / Li-polymer Battery Protection IC
A7B Series
ABSOLUTE MAXIMUM RATINGS
Items
Supply voltage
Input voltage of VM
Output voltage of CO
Output voltage of DO
Power dissipation
Operating temperature
Storage temperature
Symbol
VDD
VM
VCO
VDO
PD
Topr
Tstg
Ratings
VSS – 0.3 to VSS + 12
VDD – 28 to VDD + 0.3
VM – 0.3 to VDD + 0.3
VSS – 0.3 to VDD + 0.3
250
–40 to +85
–55 to +125
Unit
V
V
V
V
mW
°C
°C
ELECTRONICAL STATIC DISCHARGE (ESD)
A7B series are equipped ESD protection. However, please keep following conditions for preventing IC from excessive
electrical stress.
z Tip of soldering iron, all of tools and testing machines must be connected to an earth plate.
z Power supply must be put first ahead of input signal.
z All input signals must be connected to an earth plate when you do not use IC.
z Do not input beyond absolute maximum ratings even if a moment.
AnaSem Inc.
4 .......... Future of the analog world
5 Page 
Rev. E09-06
Single-cell Li-ion / Li-polymer Battery Protection IC
A7B Series
DESCRIPTION OF OPERATION
z Normal condition
This IC monitors the battery voltage (VDD) and the voltage of VM terminal, and controls charge and discharge.
If the battery voltage (VDD) is in the range from the over-discharge detection voltage (Vdc) to the over-charge
detection voltage (Vc) and the VM terminal voltage is in the range from the charge over-current detection voltage
(VIc) to the discharge over-current detection voltage (VIdc), this IC turns on both the charge and discharge
control FETs. This state is called the normal condition, and charge and discharge are possible together.
z Discharge over-current detection, Load short-circuiting detection
When the discharge current becomes equal to or higher than the specified value under the normal condition, and
if the VM terminal voltage is in the range from the discharge over current detection voltage (VIdc) to the short-
circuiting detection voltage (Vshort) and that state is maintained during more than the discharge over-current
detection delay time (tidc), this IC turns off the discharge control FET to stop discharge. This state is called the
discharge over-current condition.
At that time, if the VM terminal voltage is equal to or higher than Vshort and that state is maintained during more
than the load short-circuiting detection delay time (tshort), this IC turns off the discharge control FET to stop
discharge. This state is called the load short-circuiting detection condition.
While load is connected, in both conditions, the VM terminal voltage equals to VDD potential due to the load, but it
falls by the discharge over-current release resistance (Rdwn) when the load is removed and the resistance
between (+) and (-) terminals of battery pack (refer to “TYPICAL CONNECTION DIAGRAM”) becomes larger
than the value which enables the automatic return.
Then the VM terminal voltage becomes less than VIdc, and if that state is maintained during more than the
release delay time 1 (trel1), this IC returns to normal condition.
Note)
The resistance value between (+) and (-) terminals of battery pack for automatic return changes with battery
voltage (VDD) or VIdc. The standard is expressed with the following equation.
Resistance value for automatic return = Rdwn × (VDD / VIdc - 1)
z Charge over-current detection
When the charge current becomes equal to or higher than the specified value under the normal condition, if the
VM terminal voltage becomes less than the charge over-current detection voltage (VIc) and that state is
maintained during more than the charge over-current detection delay time (tic), this IC turns off the charge
control FET to stop charge. This state is called the charge over-current detection condition.
Then the VM terminal voltage becomes equals to or higher than VIc and that state is maintained during more
than the release delay time 1 (trel1) when the charger is removed and the load is connected, this IC returns to
the normal condition.
Note)
If the VM terminal voltage becomes equal to or less than VSS-7V(typical), the charge over-current detection
delay time (tic) changes as below.
8msec model
125msec model
1.0sec model
→ 8msec (not changed)
→ 7msec (typical)
→ 56msec (typical)
AnaSem Inc.
10 .......... Future of the analog world
11 Page | ||
| Páginas | Total 23 Páginas | |
| PDF Descargar | [ Datasheet A7B.PDF ] | |
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