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PDF C8051F930-GDI Data sheet ( Hoja de datos )

Número de pieza C8051F930-GDI
Descripción 10-Bit ADC MCU
Fabricantes Silicon Laboratories 
Logotipo Silicon Laboratories Logotipo



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No Preview Available ! C8051F930-GDI Hoja de datos, Descripción, Manual

C8051F930-GDI
Tested Single/Dual Battery, 0.9–3.6 V, 64 kB Flash,
SmaRTClock, 10-Bit ADC MCU Die in Wafer Form
Supply Voltage 0.9 to 3.6 V
- One-Cell Mode supports 0.9 to 1.8 V operation
- Two-Cell Mode supports 1.8 to 3.6 V operation
- Built-in dc-dc converter with 1.8 to 3.3 V output for
use in one-cell mode
- Built-in LDO regulator allows a high analog supply
voltage and low digital core voltage
- 2 built-in supply monitors (brownout detectors)
10-Bit Analog to Digital Converter
- 1LSB INL; no missing codes
- Programmable throughput up to 300 ksps
- 23 external inputs
- On-Chip Voltage Reference
- On-Chip PGA allows measuring voltages up to twice
the reference voltage
- 16-bit Auto-Averaging Accumulator with Burst Mode
provides increased ADC resolution
- Data dependent windowed interrupt generator
- Built-in temperature sensor
Two Comparators
- Programmable hysteresis and response time
- Configurable as wake-up or reset source
- 23 Capacitive Touch Sense inputs
6-Bit Programmable Current Reference
- Up to ± 500 A. Can be used as a bias or for gener-
ating a custom reference voltage
On-Chip Debug
- On-chip debug circuitry facilitates full-speed, non-
intrusive in-system debug (no emulator required)
- Provides breakpoints, single stepping
- Inspect/modify memory and registers
- Complete development kit
High-Speed 8051 C Core
- Pipelined instruction architecture; executes 70% of
instructions in 1 to 2 system clocks
- 25 MIPS throughput with 25 MHz clock
- Expanded interrupt handler
Memory
- 4352 bytes internal data RAM (256+4096)
- 64 kB Flash; In-system programmable in 1024-byte
sectors--1024 bytes are reserved in the 64 kB
devices
Digital Peripherals
- 24 port I/O; All 5 V tolerant with high sink current
and programmable drive strength
- Hardware SMBusTM (I2C Compatible), 2 x SPITM,
and UART serial ports available concurrently
- Four general purpose 16-bit counter/timer array with
six capture/compare modules and watchdog timer
- Hardware SmaRTClock operates down to 0.9V and
requires less than 0.5 A supply current
Clock Sources
- Internal oscillators: 24.5 MHz, 2% accuracy sup-
ports UART operation; 20 MHz low power oscillator
requires very little bias current
- External oscillator: Crystal, RC, C, or CMOS Clock
- SmaRT Clock oscillator: 32 kHz Crystal or internal
self-oscillate mode
- Can switch between clock sources on-the-fly; useful
in implementing various power saving modes
Temperature range: –40 to +85 oC
Full Technical Data Sheet
- C8051F93x-C8051F92x
ANALOG
DIGITAL I/O
PERIPHERALS
A 10-bit
M
U
300 ksps
X ADC
IREF
++
VREF
TEMP
SENSOR VREG VOLTAGE
COMPARATORS
UART
SMBus
2 x SPI
PCA
Timer 0
Timer 1
Timer 2
Timer 3
CRC
Port 0
Port 1
Port 2
24.5 MHz PRECISION
INTERNAL OSCILLATOR
20 MHz LOW POWER
INTERNAL OSCILLATOR
External Oscillator
HARDWARE SmaRTClock
HIGH-SPEED CONTROLLER CORE
64 kB
ISP FLASH
FLEXIBLE
INTERRUPTS
8051 CPU
(25 MIPS)
DEBUG
CIRCUITRY
4352 B
SRAM
POR WDT
Rev. 1.3 11/13
Copyright © 2013 by Silicon Laboratories
C8051F930-GDI

1 page




C8051F930-GDI pdf
C8051F930-GDI
Name
P0.5
Table 2.1. Pin Definitions for the C8051F930-GDI (Continued)
Physical
Pad
Number
Type
Description
30 D I/O or Port 0.5. See Port I/O section of the C8051F93x-C8051F92x data
A In sheet for a complete description.
RX
P0.6
D In
UART RX Pin. See Port I/O section of the C8051F93x-C8051F92x
data sheet for a complete description.
29 D I/O or Port 0.6. See Port I/O section of the C8051F93x-C8051F92x data
A In sheet for a complete description.
CNVSTR
P0.7
IREF0
P1.0
D In
External Convert Start Input for ADC0. See ADC0 section of the
C8051F93x-C8051F92x data sheet for a complete description.
28 D I/O or Port 0.7. See Port I/O section of the C8051F93x-C8051F92x data
A In sheet for a complete description.
A Out
IREF0 Output. See IREF section of the C8051F93x-C8051F92x data
sheet for complete description.
27 D I/O or Port 1.0. See Port I/O section of the C8051F93x-C8051F92x data
A In sheet for a complete description. May also be used as SCK for SPI1.
AD0
P1.1
AD1
P1.2
AD2
P1.3
AD3
P1.4
D I/O Address/Data 0.
26 D I/O or Port 1.1. See Port I/O section of the C8051F93x-C8051F92x data
A In sheet for a complete description.
May also be used as MISO for SPI1.
D I/O
Address/Data 1.
25 D I/O or Port 1.2. See Port I/O section of the C8051F93x-C8051F92x data
A In sheet for a complete description.
May also be used as MOSI for SPI1.
D I/O
Address/Data 2.
24 D I/O or Port 1.3. See Port I/O section of the C8051F93x-C8051F92x data
A In sheet for a complete description.
May also be used as NSS for SPI1.
D I/O
Address/Data 3.
21 D I/O or Port 1.4. See Port I/O section of the C8051F93x-C8051F92x data
A In sheet for a complete description.
AD4
D I/O
Address/Data 4.
Rev. 1.3
5

5 Page





C8051F930-GDI arduino
C8051F930-GDI
Table 3.2. Wafer and Die Information
Wafer ID
Wafer Dimensions
Die Dimensions
Wafer Thickness (with backgrind)
Wafer Thickness (no backgrind)
Wafer Identification
Scribe Line Width
Die Per Wafer*
Passivation
Wafer Packaging Detail
Bond Pad Dimensions
Maximum Processing Temperature
Electronic Die Map Format
Bond Pad Pitch Minimum
C8051F930G
8 in
2.28 mm x 2.28 mm
12 mil ±1 mil
28.54 mil ±1 mil, 725 µm
Notch
80 µm
Contact Sales for info
Standard
Wafer Jar
60 µm x 60 µm
250 °C
.txt
142 µm
*Note: This is the Expected Known Good Die yielded per wafer and represents
the batch order quantity (one wafer).
Rev. 1.3
11

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