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PC28F064M29EWLX Schematic ( PDF Datasheet ) - Micron

Teilenummer PC28F064M29EWLX
Beschreibung Parallel NOR Flash Embedded Memory
Hersteller Micron
Logo Micron Logo 




Gesamt 30 Seiten
PC28F064M29EWLX Datasheet, Funktion
32Mb, 64Mb, 128Mb: 3V Embedded Parallel NOR Flash
Features
Parallel NOR Flash Embedded Memory
JR28F032M29EWXX; PZ28F032M29EWXX; JS28F064M29EWXX
PC28F064M29EWXX; JR28F064M29EWXX; PZ28F064M29EWXX
JS28F128M29EWXX; PC28F128M29EWXX; RC28F128M29EWXX
Features
• Supply voltage
– VCC = 2.7–3.6V (program, erase, read)
– VCCQ = 1.65–3.6V (I/O buffers)
• Asynchronous random or page read
– Page size: 8 words or 16 bytes
– Page access: 25ns
– Random access: 60ns (BGA); 70ns (TSOP)
• Buffer program: 256-word MAX program buffer
• Program time
– 0.56µs per byte (1.8 MB/s TYP when using 256-
word buffer size in buffer program without VPPH)
– 0.31µs per byte (3.2 MB/s TYP when using 256-
word buffer size in buffer program with VPPH)
• Memory organization
– 32Mb: 64 main blocks, 64KB each, or eight 8KB
boot blocks (top or bottom) and 63 main blocks,
64KB each
– 64Mb: 128 main blocks, 64KB each, or eight 8KB
boot blocks (top or bottom) and 127 main blocks,
64 KB each
– 128Mb: 128 main blocks, 128KB each
• Program/erase controller
– Embedded byte/word program algorithms
• Program/erase suspend and resume capability
– READ operation on any block during a PRO-
GRAM SUSPEND operation
– READ or PROGRAM operation on one block dur-
ing an ERASE SUSPEND operation on another
block
• BLANK CHECK operation to verify an erased block
• Unlock bypass, block erase, chip erase, and write to
buffer capability
– Fast buffered/batch programming
– Fast block and chip erase
• VPP/WP# pin protection
– VPPH voltage on VPP to accelerate programming
performance
– Protects highest/lowest block (H/L uniform) or
top/bottom two blocks (T/B boot)
• Software protection
– Volatile protection
– Nonvolatile protection
– Password protection
– Password access
• Extended memory block
– 128-word (256-byte) block for permanent secure
identification
– Program or lock implemented at the factory or by
the customer
• Low-power consumption: Standby mode
• JESD47H-compliant
– 100,000 minimum ERASE cycles per block
– Data retention: 20 years (TYP)
• 65nm single-bit cell process technology
• Packages (JEDEC-standard)
– 56-pin TSOP (128Mb, 64Mb)
– 48-pin TSOP (64Mb, 32Mb)
– 64-ball FBGA (128Mb, 64Mb)
– 48-ball BGA (64Mb, 32Mb)
• Green packages available
– RoHS-compliant
– Halogen-free
• Operating temperature
– Ambient: –40°C to +85°C
PDF: 09005aef84dc44a7
m29ew_32Mb-128Mb.pdf - Rev. B 11/12 EN
1 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2012 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
http://www.Datasheet4U.com






PC28F064M29EWLX Datasheet, Funktion
32Mb, 64Mb, 128Mb: 3V Embedded Parallel NOR Flash
Features
List of Figures
Figure 1: Logic Diagram ................................................................................................................................... 8
Figure 2: 56-Pin TSOP (Top View) .................................................................................................................... 9
Figure 3: 48-Pin TSOP (Top View) .................................................................................................................. 10
Figure 4: 48-Ball BGA (Top and Bottom Views) ............................................................................................... 11
Figure 5: 64-Ball Fortified BGA (Top and Bottom Views) .................................................................................. 12
Figure 6: Data Polling Flowchart .................................................................................................................... 24
Figure 7: Toggle Bit Flowchart ........................................................................................................................ 25
Figure 8: Status Register Polling Flowchart ..................................................................................................... 26
Figure 9: Lock Register Program Flowchart ..................................................................................................... 28
Figure 10: Boundary Condition of Program Buffer Size .................................................................................... 39
Figure 11: WRITE TO BUFFER PROGRAM Flowchart ...................................................................................... 40
Figure 12: Program/Erase Nonvolatile Protection Bit Algorithm ...................................................................... 52
Figure 13: Software Protection Scheme .......................................................................................................... 57
Figure 14: Power-Up Timing .......................................................................................................................... 64
Figure 15: Reset AC Timing – No PROGRAM/ERASE Operation in Progress ...................................................... 65
Figure 16: Reset AC Timing During PROGRAM/ERASE Operation .................................................................... 65
Figure 17: AC Measurement Load Circuit ....................................................................................................... 67
Figure 18: AC Measurement I/O Waveform ..................................................................................................... 67
Figure 19: Random Read AC Timing (8-Bit Mode) ........................................................................................... 71
Figure 20: Random Read AC Timing (16-Bit Mode) ......................................................................................... 71
Figure 21: BYTE# Transition Read AC Timing .................................................................................................. 72
Figure 22: Page Read AC Timing (16-Bit Mode) ............................................................................................... 72
Figure 23: WE#-Controlled Program AC Timing (8-Bit Mode) .......................................................................... 74
Figure 24: WE#-Controlled Program AC Timing (16-Bit Mode) ......................................................................... 75
Figure 25: CE#-Controlled Program AC Timing (8-Bit Mode) ........................................................................... 77
Figure 26: CE#-Controlled Program AC Timing (16-Bit Mode) ......................................................................... 78
Figure 27: Chip/Block Erase AC Timing (8-Bit Mode) ...................................................................................... 79
Figure 28: Accelerated Program AC Timing ..................................................................................................... 80
Figure 29: Data Polling AC Timing .................................................................................................................. 80
Figure 30: Toggle/Alternative Toggle Bit Polling AC Timing (8-Bit Mode) .......................................................... 81
Figure 31: 56-Pin TSOP – 14mm x 20mm ........................................................................................................ 83
Figure 32: 48-Pin TSOP – 12mm x 20mm ........................................................................................................ 84
Figure 33: 48-Ball BGA – 6mm x 8mm ............................................................................................................. 85
Figure 34: 64-Ball Fortified BGA – 11mm x 13mm ........................................................................................... 86
PDF: 09005aef84dc44a7
m29ew_32Mb-128Mb.pdf - Rev. B 11/12 EN
6 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2012 Micron Technology, Inc. All rights reserved.

6 Page









PC28F064M29EWLX pdf, datenblatt
32Mb, 64Mb, 128Mb: 3V Embedded Parallel NOR Flash
Signal Assignments
Figure 5: 64-Ball Fortified BGA (Top and Bottom Views)
12 34 567 8
A
RFU A3
A7 RY/BY# WE# A9 A13 RFU
B
RFU A4 A17 VPP/WP# RST# A8 A12 A22
C
RFU A2 A6 A18 A21 A10 A14 RFU
D
RFU A1 A5 A20 A19 A11 A15 VCCQ
E
RFU A0 D0 D2 D5 D7 A16 VSS
F
VCCQ CE# D8 D10 D12 D14 BYTE# RFU
G
RFU OE# D9 D11 VCC D13 D15/A-1 RFU
H
RFU VSS D1 D3 D4 D6 VSS RFU
8 7 65 432 1
RFU A13 A9 WE# RY/BY# A7
A
A3 RFU
B
A22 A12 A8 RST#VPP/WP# A17 A4 RFU
C
RFU A14 A10 A21 A18 A6 A2 RFU
D
VCCQ A15 A11 A19 A20 A5 A1 RFU
E
VSS A16 D7 D5 D2 D0 A0 RFU
F
RFU BYTE# D14 D12 D10 D8 CE# VCCQ
G
RFU D15/A-1 D13 VCC D11 D9 OE# RFU
H
RFU VSS D6 D4 D3 D1 VSS RFU
Fortified BGA
Top view – ball side down
Fortified BGA
Bottom view – ball side up
Notes:
1. A-1 is the least significant address bit in x8 mode.
2. A21 is valid for 64Mb and above; otherwise, it is RFU.
3. A22 is valid for 128Mb and above; otherwise, it is RFU.
4. RFU = Reserved for future use.
PDF: 09005aef84dc44a7
m29ew_32Mb-128Mb.pdf - Rev. B 11/12 EN
12
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2012 Micron Technology, Inc. All rights reserved.

12 Page





SeitenGesamt 30 Seiten
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