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PDF AD9364 Data sheet ( Hoja de datos )
| Número de pieza | AD9364 | |
| Descripción | RF Agile Transceiver | |
| Fabricantes | Analog Devices | |
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Data Sheet
FEATURES
RF 1 × 1 transceiver with integrated 12-bit DACs and ADCs
Band: 70 MHz to 6.0 GHz
Supports time division duplex (TDD) and frequency division
duplex (FDD) operation
Tunable channel bandwidth (BW): <200 kHz to 56 MHz
3-band receiver: 3 differential or 6 single-ended inputs
Superior receiver sensitivity with a noise figure of <2.5 dB
Rx gain control
Real-time monitor and control signals for manual gain
Independent automatic gain control
2-band differential output transmitter
Highly linear broadband transmitter
Tx EVM: ≤−40 dB
Tx noise: ≤−157 dBm/Hz noise floor
Tx monitor: ≥66 dB dynamic range with 1 dB accuracy
Integrated fractional-N synthesizers
2.4 Hz maximum local oscillator (LO) step size
Multichip synchronization
CMOS/LVDS digital interface
APPLICATIONS
Point to point communication systems
Femtocell/picocell/microcell base stations
General-purpose radio systems
GENERAL DESCRIPTION
The AD9364 is a high performance, highly integrated radio fre-
quency (RF) Agile Transceiver™ designed for use in 3G and 4G base
station applications. Its programmability and wideband capability
make it ideal for a broad range of transceiver applications.
The device combines an RF front end with a flexible mixed-signal
baseband section and integrated frequency synthesizers, simpli-
fying design-in by providing a configurable digital interface to a
processor. The AD9364 operates in the 70 MHz to 6.0 GHz range,
covering most licensed and unlicensed bands. Channel bandwidths
from less than 200 kHz to 56 MHz are supported.
The direct conversion receiver has state-of-the-art noise figure
and linearity. The receive (Rx) subsystem includes independent
automatic gain control (AGC), dc offset correction, quadrature
correction, and digital filtering, thereby eliminating the need for
these functions in the digital baseband. The AD9364 also has
flexible manual gain modes that can be externally controlled.
Two high dynamic range ADCs digitize the received I and Q
signals and pass them through configurable decimation filters
RF Agile Transceiver
AD9364
FUNCTIONAL BLOCK DIAGRAM
RXB_P,
RXB_N
RXA_P,
RXA_N
RXC_P,
RXC_N
TX_MON
TXA_P,
TXA_N
TXB_P,
TXB_N
SPI
CTRL
AD9364
Rx LO
Tx LO
ADC
DAC
CTRL
GPO
PLLs
P0_[D11:D0]/
TX_[D5:D0]
P1_[D11:D0]/
RX_[D5:D0]
RADIO
SWITCHING
CLK_OUT
AUXADC AUXDACx XTALN
NOTES
1. SPI, CTRL, P0_[D11:D0]/TX_[D5:D0], P1_[D11:D0]/RX_[D5:D0],
AND RADIO SWITCHING CONTAIN MULTIPLE PINS.
Figure 1.
and 128-tap FIR filters to produce a 12-bit output signal at the
appropriate sample rate.
The transmitter uses a direct conversion architecture that achieves
high modulation accuracy with ultralow noise. This transmitter
design produces a Tx EVM of ≤−40 dB, allowing significant system
margin for the external power amplifier (PA) selection. The on-
board transmit (Tx) power monitor can be used as a power
detector, enabling highly accurate Tx power measurements.
The fully integrated phase-locked loops (PLLs) provide low
power fractional-N frequency synthesis for all Rx and Tx channels.
All VCO and loop filter components are integrated.
The core of the AD9364 can be powered directly from a 1.3 V
regulator. The IC is controlled via a standard 4-wire serial port and
four real-time input control pins. Comprehensive power-down
modes are included to minimize power consumption during
normal use. The AD9364 is packaged in a 10 mm ×10 mm,
144-ball chip scale packageball grid array (CSP_BGA).
Rev. B
Document Feedback
Information furnishedb yA nalogD evices isbe lieved to bea ccuratean dr eliable.H owever,n o
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
licenseisgranted by implicationorotherwise underany patentorpatentrightsofAnalogDevices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One T echnology Way, P .O. B ox 91 06, Nor wood, MA 020 62-9106, U. S.A.
Tel: 781.329.4700 ©2013–2014 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
http://www.Datasheet4U.com
1 page  
Data Sheet
Parameter1
Output Voltage
Minimum
Maximum
Output Current
DIGITAL SPECIFICATIONS (CMOS)
Logic Inputs
Input Voltage
High
Low
Input Current
High
Low
Logic Outputs
Output Voltage
High
Low
DIGITAL SPECIFICATIONS (LVDS)
Logic Inputs
Input Voltage Range
Symbol Min
Typ
0.5
VDD_GPO − 0.3
10
VDD_INTERFACE × 0.8
0
−10
−10
VDD_INTERFACE × 0.8
825
Input Differential Voltage
Threshold
Receiver Differential Input
Impedance
Logic Outputs
Output Voltage
High
Low
Output Differential Voltage
−100
1025
150
100
Output Offset Voltage
GENERAL-PURPOSE OUTPUTS
Output Voltage
High
Low
Output Current
SPI TIMING
SPI_CLK
Period
Pulse Width
SPI_ENB Setup to First SPI_CLK
Rising Edge
Last SPI_CLK Falling Edge to
SPI_ENB Hold
SPI_DI
Data Input Setup to
SPI_CLK
Data Input Hold to SPI_CLK
SPI_CLK Rising Edge to Output
Data Delay
4-Wire Mode
3-Wire Mode
Bus Turnaround Time, Read
tCP
tMP
tSC
tHC
tS
tH
tCO
tCO
tHZM
VDD_GPO × 0.8
20
9
1
0
2
1
3
3
tH
1200
10
Bus Turnaround Time, Read
tHZS
0
Max Unit
V
V
mA
VDD_INTERFACE
V
VDD_INTERFACE × 0.2 V
+10 μA
+10 μA
V
VDD_INTERFACE × 0.2 V
1575
+100
mV
mV
Ω
1375
VDD_GPO × 0.2
8
8
tCO (max)
tCO (max)
mV
mV
mV
mV
V
V
mA
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AD9364
Test Conditions/Comments
Each differential input in the
pair
Programmable in 75 mV
steps
VDD_INTERFACE = 1.8 V
After baseband processor
(BBP) drives the last address
bit
After the AD9364 drives the
last databit
Rev. B | Page 5 of 32
5 Page 
Data Sheet
AD9364
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1 2 3 4 5 6 7 8 9 10 11 12
A VSSA
B VSSA
C VSSA
VSSA
VSSA
VSSA
NC
AUXDAC1
AUXDAC2
VSSA
GPO_3
TEST/
ENABLE
VSSA
GPO_2
VSSA
GPO_1
VDDA1P3_ VDDA1P3_ VDDA1P3_ VDDA1P3_ VDDA1P1_
RX_TX
RX_TX
RX_TX
RX_TX
TX_VCO
GPO_0
VDD_GPO
VDDA1P3_
TX_LO
VDDA1P3_
TX_VCO_
LDO
TX_VCO_
LDO_OUT
TX_EXT_
LO_IN
VSSA
CTRL_IN0 CTRL_IN1
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
D
VSSA
VDDA1P3_
RX_RF
VDDA1P3_
RX_TX
CTRL_OUT0
CTRL_IN3
CTRL_IN2
P0_D9/
TX_D4_P
P0_D7/
TX_D3_P
P0_D5/
TX_D2_P
P0_D3/
TX_D1_P
P0_D1/
TX_D0_P
VSSD
E
VSSA
VDDA1P3_
RX_LO
VDDA1P3_
TX_LO_ CTRL_OUT1 CTRL_OUT2 CTRL_OUT3
P0_D11/
TX_D5_P
P0_D8/
TX_D4_N
P0_D6/
TX_D3_N
P0_D4/
TX_D2_N
P0_D2/
TX_D1_N
P0_D0/
TX_D0_N
BUFFER
VDDA1P3_
F VSSA RX_VCO_ VSSA CTRL_OUT6 CTRL_OUT5 CTRL_OUT4 VSSD
LDO
P0_D10/
TX_D5_N
VSSD
FB_CLK_P
VSSD
VDDD1P3_
DIG
G
RX_EXT_
LO_IN
RX_VCO_ VDDA1P1_ CTRL_OUT7 EN_AGC
LDO_OUT RX_VCO
ENABLE
RX_ RX_ TX_ FB_CLK_N
FRAME_N FRAME_P FRAME_P
DATA_
CLK_P
VSSD
H RXB_P
VSSA
VSSA
TXNRX
SYNC_IN
VSSA
VSSD
P1_D11/
TX_
RX_D5_P FRAME_N
VSSD
DATA_
CLK_N
VDD_
INTERFACE
J RXB_N
VSSA
VDDA1P3_
RX_SYNTH
SPI_DI
SPI_CLK
CLK_OUT
P1_D10/
RX_D5_N
P1_D9/
RX_D4_P
P1_D7/
RX_D3_P
P1_D5/
RX_D2_P
P1_D3/
RX_D1_P
P1_D1/
RX_D0_P
K RXC_P
VSSA
VDDA1P3_ VDDA1P3_
TX_SYNTH
BB
RESETB
SPI_ENB
P1_D8/
RX_D4_N
P1_D6/
RX_D3_N
P1_D4/
RX_D2_N
P1_D2/
RX_D1_N
P1_D0/
RX_D0_N
VSSD
L RXC_N
VSSA
VSSA
RBIAS
AUXADC
SPI_DO
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
M RXA_P
RXA_N
NC
VSSA
TX_MON
VSSA
TXA_P
TXA_N
TXB_P
TXB_N
XTALP
XTALN
ANALOG I/O
DIGITAL I/O
NO CONNECT
DC POWER
GROUND
Figure 2. Pin Configuration, Top View
Table 13. Pin Function Descriptions
Pin No.
Type1 Mnemonic
A1, A2, A4 to
A6, B1, B2,
B12, C1, C2,
C7 to C12, D1,
E1, F1, F3, H2,
H3, H6, J2, K2,
L2, L3, L7 to
L12, M4, M6
I
VSSA
A3, M3
NC NC
A7 to A10, D3 I
VDDA1P3_RX_TX
A11 I VDDA1P1_TX_VCO
A12 I TX_EXT_LO_IN
B3
B4 to B7
B8
O AUXDAC1
O GPO_3 to GPO_0
I VDD_GPO
B9 I VDDA1P3_TX_LO
B10 I VDDA1P3_TX_VCO_LDO
B11 O TX_VCO_LDO_OUT
C3 O AUXDAC2
C4 I TEST/ENABLE
Description
Analog Ground. Tie these pins directly to the VSSD digital ground on the printed
circuit board (one ground plane).
No Connect. Do not connect to these pins.
1.3 V Supply Input.
Transmit VCO Supply Input. Connect to B11.
External Transmit Local Oscillator (LO) Input. When this pin is unused, tie it to
ground.
Auxiliary DAC 1 Output.
3.3 V Capable General-Purpose Outputs.
2.5 V to 3.3 V Supply for the Auxiliary DAC and General-Purpose Output Pins.
When the VDD_GPO supply is not used, this supply must be set to 1.3 V.
Transmit LO 1.3 V Supply Input.
Transmit VCO LDO 1.3 V Supply Input. Connect to B9.
Transmit VCO LDO Output. Connect B11 to A11 and a 1 μF bypass capacitor in
series with a 1 Ω resistor to ground.
Auxiliary DAC 2 Output.
Test Input. Ground this pin for normal operation.
Rev. B | Page 11 of 32
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9364.PDF ] | |
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