|
|
PDF AD9652 Data sheet ( Hoja de datos )
| Número de pieza | AD9652 | |
| Descripción | 3.3V / 1.8V Dual Analog-to-Digital Converter | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de AD9652 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
Data Sheet
16-Bit, 310 MSPS, 3.3 V/1.8 V Dual
Analog-to-Digital Converter (ADC)
AD9652
FEATURES
High dynamic range
SNR = 75.0 dBFS at 70 MHz (AIN = −1 dBFS)
SFDR = 87 dBc at 70 MHz (AIN = −1 dBFS)
Noise spectral density (NSD) = −156.7 dBFS/Hz input noise
at −1 dBFS at 70 MHz
NSD = −157.6 dBFS/Hz for small signal at −7dBFS at 70 MHz
90 dB channel isolation/crosstalk
On-chip dithering (improves small signal linearity)
Excellent IF sampling performance
SNR = 73.7 dBFS at 170 MHz (AIN = −1 dBFS)
SFDR = 85 dBc at 170 MHz (AIN = −1 dBFS)
Full power bandwidth of 465 MHz
On-chip 3.3 V buffer
Programmable input span of 2 V p-p to 2.5 V p-p (default)
Differential clock input receiver with 1, 2, 4, and 8 integer
inputs (clock divider input accepts up to 1.24 GHz)
Internal ADC clock duty cycle stabilizer
SYNC input allows multichip synchronization
Total power consumption: 2.16 W
3.3 V and 1.8 V supply voltages
DDR LVDS (ANSI-644 levels) outputs
Serial port control
Energy saving power-down modes
APPLICATIONS
Military radar and communications
Multimode digital receivers (3G or 4G)
Test and instrumentation
Smart antenna systems
GENERAL DESCRIPTION
The AD9652 is a dual, 16-bit analog-to-digital converter (ADC)
with sampling speeds of up to 310 MSPS. It is designed to
support demanding, high speed signal processing applications
that require exceptional dynamic range over a wide input
frequency range (up to 465 MHz). Its exceptional low noise
floor of −157.6 dBFS and large signal spurious-free dynamic
range (SFDR) performance (exceeding 85 dBFS, typical) allows
low level signals to be resolved in the presence of large signals.
The dual ADC cores feature a multistage, pipelined architecture
with integrated output error correction logic. A high performance
on-chip buffer and internal voltage reference simplify the inter-
face to external driving circuitry while preserving the exceptional
performance of the ADC.
The AD9652 can support input clock frequencies of up to
1.24 GHz with a 1, 2, 4, and 8 integer clock divider used to
generate the ADC sample clock. A duty cycle stabilizer is
provided to compensate for variations in the ADC clock duty
Rev. A
Document Feedback
Information furnishedb yA nalogD evices isb elieved to beac curatea ndrel iable.H owever,n o
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is grantedby implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property oftheir respective owners.
FUNCTIONAL BLOCK DIAGRAM
AVDD3 AVDD SDIO SCLK CSB
DRVDD
VIN+A
VIN–A
AD9652
ADC
SPI
PROGRAMMING DATA
DDR DATA
INTERLEAVER 16
LVDS OUTPUT
DRIVER
OR+, OR–
D15± (MSB)
TO
D0± (LSB)*
VREF
SENSE
VCM
RBIAS
VIN–B
VIN+B
REF
SELECT
ADC
DIVIDE 1
TO 8
DUTY CYCLE
DCO
STABILIZER GENERATION
CLK+
CLK–
DCO+
DCO–
MULTICHIP
SYNC
AGND
SYNC
PDWN
*THESE PINS ARE FOR CHANNEL A AND CHANNEL B.
Figure 1.
cycle. The 16-bit output data (with an overrange bit) from each
ADC is interleaved onto a single LVDS output port along with a
double data rate (DDR) clock. Programming for setup and control
are accomplished using a 3-wire SPI-compatible serial interface.
The AD9652 is available in a 144-ball CSP_BGA and is
specified over the industrial temperature range of −40°C to
+85°C. This product is protected by pending U.S. patents.
PRODUCT HIGHLIGHTS
1. Integrated dual, 16-bit, 310 MSPS ADCs.
2. On-chip buffer simplifies ADC driver interface.
3. Operation from 3.3 V and 1.8 V supplies and a separate
digital output driver supply accommodating LVDS outputs.
4. Proprietary differential input maintains excellent signal-to-
noise ratio (SNR) performance for input frequencies of up
to 485 MHz.
5. SYNC input allows synchronization of multiple devices.
6. Three-wire, 3.3 V or 1.8 V SPI port for register programming
and readback.
One T echnology Way, P .O. B ox 91 06, Norwood, M A 020 62-9106, U .S.A.
Tel: 781.329.4700
©2014 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
http://www.Datasheet4U.com
1 page  
Data Sheet
AD9652
Parameter1
WORST OTHER (NOT INCLUDING 2nd or 3rd HARMONIC)
fIN = 30 MHz (Use Nyquist 1 Settings)
fIN = 70 MHz (Use Nyquist 1 Settings)
fIN = 70 MHz (Use Nyquist 1 Settings, with Dither Enabled)
fIN = 170 MHz (Use Nyquist 2 Settings)
fIN = 170 MHz (Use Nyquist 2 Settings, with Dither Enabled)
fIN = 305 MHz (Use Nyquist 2 Settings)
fIN = 400 MHz (Use Nyquist 3 Settings)
TWO-TONE SFDR
fIN = 70.1 MHz (−7 dBFS ), 72.1 MHz (−7 dBFS )
fIN = 184.12 MHz (−7 dBFS ), 187.12 MHz (−7 dBFS )
CROSSTALK2
FULL POWER BANDWIDTH3
NOISE BANDWIDTH4
Temperature
VREF = 1 V
Min Typ Max
VREF = 1.25 V,
Default
Min Typ Max
25°C
25°C
Full
25°C
25°C
25°C
25°C
25°C
−101
−99
−100
−91
−90
−98
−92
−102
−98
−100
−90
−95
−97
−91
−90
−86
25°C
93
25°C
83
Full 90 90
25°C 485 485
25°C 650 650
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.
2 Crosstalk is measured at 100 MHz with −1.0 dBFS on one channel and no input on the alternate channel.
3 Full power bandwidth is the bandwidth of operation in which proper ADC performance can be achieved.
4 Noise bandwidth is the −3 dB bandwidth for the ADC inputs across which noise can enter the ADC and is not attenuated internally.
Unit
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dB
MHz
MHz
DIGITAL SPECIFICATIONS
AVDD3 = 3.3 V, AVDD = AVDD_CLK = 1.8 V, SPIVDD = DRVDD = 1.8 V,sample rate = 310 MSPS (clock input = 1240 MHz, AD9652
divided by 4), VIN = −1.0 dBFS differential input, 2.5 V p-p full-scale input range, DCS enabled, dither disabled, unless otherwise noted.
Table 3.
Parameter
DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)
Logic Compliance
Differential Input Voltage
Input Voltage Range
Internal Common-Mode Bias
Input Common-Mode Range
High Level Input Current
Low Level Input Current
Input Capacitance1
Input Resistance1
SYNC INPUT
Logic Compliance
Internal Bias
Input Voltage Range
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
Input Resistance
Test Conditions/Comments Temperature Min Typ Max
Unit
CMOS/LVDS/LVPECL
Full 0.3 3.6 V p-
p
Full
AGND
AVDD_CLK V
Full 0.9 V
Full 0.9 1.4 V
Full
+10
+145
µA
Full
−155
−15 µA
Full 5 pF
Full 10 kΩ
CMOS/LVDS
Full 0.9 V
Full
AGND
AVDD_CLK V
Full 1.2 AVDD_CLK V
Full
AGND
0.6
V
Full
−15
+110
µA
Full
−105
+15 µA
Full 1.5 pF
Full 16 kΩ
Rev. A | Page 5 of 36
5 Page 
Data Sheet
Pin No.
J3
J4
J5
J6
J7
J9
J10
ADC Analog
A9
A8
A4
A5
A2
A1 RBIAS
A12
A11
E1
D1
Digital Inputs
F1
G1
H1 P
Digital Outputs
J2
J1
K2
K1
L1
M1
L2
M2
L3
M3
L4
M4
L5
M5
L6
M6
L7
M7
L8
M8
L9
M9
L10
M10
L11
M11
Mnemonic
DRGND
DRGND
DRGND
DRGND
DRGND
DRGND
DRGND
VIN+A
VIN−A
VIN+B
VIN−B
VCM
VREF
SENSE
CLK+
CLK−
TEST
SYNC
DWN
D0+
D0−
D1+
D1−
D2+
D2−
D3+
D3−
D4+
D4−
D5+
D5−
D6+
D6−
D7+
D7−
D8+
D8−
D9+
D9−
D10+
D10−
D11+
D11−
D12+
D12−
AD9652
Type
Digital Ground
Digital Ground
Digital Ground
Digital Ground
Digital Ground
Digital Ground
Digital Ground
Description
Digital and Output Driver Ground Reference.
Digital and Output Driver Ground Reference.
Digital and Output Driver Ground Reference.
Digital and Output Driver Ground Reference.
Digital and Output Driver Ground Reference.
Digital and Output Driver Ground Reference.
Digital and Output Driver Ground Reference.
Input
Input
Input
Input
Output
Output
Input/Output
Input
Input
Input
Differential Analog Input Pin (+) for Channel A.
Differential Analog Input Pin (−) for Channel A.
Differential Analog Input Pin (+) for Channel B.
Differential Analog Input Pin (−) for Channel B.
Common-Mode Level Bias Output for Analog Inputs. Decouple
this pin to ground using a 0.1 μF capacitor.
External Bias Resister Connection. A 10 kΩ resister must be
connected between this pin and analog ground (AGND).
Voltage Reference Input/Output.
Reference Mode Selection (See Table 12).
ADC Clock Input (True).
ADC Clock Input (Complement).
Input
Input
Input
Pull-Down. Unused digital input, pull to ground through a 50 Ω
resistor.
Digital Input Clock Synchronization Pin. Tie low if unused.
Power-Down Input (Active High). The operation of this pin
depends on the SPI mode and can be configured as power-down
or standby (see Register 0x08 in Table 17).
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Channel A/Channel B LVDS Output Data 0 (True, LSB).
Channel A/Channel B LVDS Output Data 0 (Complement, LSB).
Channel A/Channel B LVDS Output Data 1 (True).
Channel A/Channel B LVDS Output Data 1 (Complement).
Channel A/Channel B LVDS Output Data 2 (True).
Channel A/Channel B LVDS Output Data 2 (Complement).
Channel A/Channel B LVDS Output Data 3 (True).
Channel A/Channel B LVDS Output Data 3 (Complement).
Channel A/Channel B LVDS Output Data 4 (True).
Channel A/Channel B LVDS Output Data 4 (Complement).
Channel A/Channel B LVDS Output Data 5 (True).
Channel A/Channel B LVDS Output Data 5 (Complement).
Channel A/Channel B LVDS Output Data 6 (True).
Channel A/Channel B LVDS Output Data 6 (Complement).
Channel A/Channel B LVDS Output Data 7 (True).
Channel A/Channel B LVDS Output Data 7 (Complement).
Channel A/Channel B LVDS Output Data 8 (True).
Channel A/Channel B LVDS Output Data 8 (Complement).
Channel A/Channel B LVDS Output Data 9 (True).
Channel A/Channel B LVDS Output Data 9 (Complement).
Channel A/Channel B LVDS Output Data 10 (True).
Channel A/Channel B LVDS Output Data 10 (Complement).
Channel A/Channel B LVDS Output Data 11 (True).
Channel A/Channel B LVDS Output Data 11 (Complement).
Channel A/Channel B LVDS Output Data 12 (True).
Channel A/Channel B LVDS Output Data 12 (Complement).
Rev. A | Page 11 of 36
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9652.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| AD9650 | 1.8 V Dual Analog-to-Digital Converter (ADC) | Analog Devices |
| AD9652 | 3.3V / 1.8V Dual Analog-to-Digital Converter | Analog Devices |
| AD9653 | Serial LVDS 1.8V Analog-to-Digital Converter | Analog Devices |
| AD9655 | 1.8V Analog-to-Digital Converter | Analog Devices |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |