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PDF AD9653 Data sheet ( Hoja de datos )
| Número de pieza | AD9653 | |
| Descripción | Serial LVDS 1.8V Analog-to-Digital Converter | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Data Sheet
Quad, 16-Bit, 125 MSPS, Serial LVDS 1.8 V
Analog-to-Digital Converter
AD9653
FEATURES
1.8 V supply operation
Low power: 164 mW per channel at 125 MSPS
SNR = 76.5 dBFS at 70 MHz (2.0 V p-p input span)
SNR = 77.5 dBFS at 70 MHz (2.6 V p-p input span)
SFDR = 90 dBc (to Nyquist, 2.0 V p-p input span)
DNL = ±0.7 LSB; INL = ±3.5 LSB (2.0 V p-p input span)
Serial LVDS (ANSI-644, default) and low power, reduced
range option (similar to IEEE 1596.3)
650 MHz full power analog bandwidth
2 V p-p input voltage range (supports up to 2.6 V p-p)
Serial port control
Full chip and individual channel power-down modes
Flexible bit orientation
Built-in and custom digital test pattern generation
Multichip sync and clock divider
Programmable output clock and data alignment
Standby mode
APPLICATIONS
Medical ultrasound and MRI
High speed imaging
Quadrature radio receivers
Diversity radio receivers
Test equipment
GENERAL DESCRIPTION
The AD9653 is a quad, 16-bit, 125 MSPS analog-to-digital con-
verter (ADC) with an on-chip sample-and-hold circuit
designed for low cost, low power, small size, and ease of use.
The product operates at a conversion rate of up to 125 MSPS
and is optimized for outstanding dynamic performance and low
power in applications where a small package size is critical.
The ADC requires a single 1.8 V power supply and LVPECL-/
CMOS-/LVDS-compatible sample rate clock for full performance
operation. No external reference or driver components are
required for many applications.
The ADC automatically multiplies the sample rate clock for the
appropriate LVDS serial data rate. A data clock output (DCO) for
capturing data on the output and a frame clock output (FCO)
for signaling a new output byte are provided. Individual-channel
power-down is supported and typically consumes less than 2 mW
when all channels are disabled. The ADC contains several features
designed to maximize flexibility and minimize system cost, such
FUNCTIONAL BLOCK DIAGRAM
AVDD
PDWN
DRVDD
VIN+A
VIN–A
16
PIPELINE
DIGITAL
ADC
SERIALIZER
VIN+B
VIN–B
RBIAS
VREF
SENSE
AGND
VIN+C
VIN–C
16
PIPELINE
DIGITAL
ADC
SERIALIZER
REF
SELECT
1V AD9653
16
PIPELINE
DIGITAL
ADC
SERIALIZER
VIN+D
VIN–D
16
PIPELINE
DIGITAL
ADC
SERIALIZER
VCM
SERIAL PORT
INTERFACE
CLOCK
MANAGEMENT
SERIAL
LVDS
SERIAL
LVDS
SERIAL
LVDS
SERIAL
LVDS
SERIAL
LVDS
SERIAL
LVDS
SERIAL
LVDS
SERIAL
LVDS
D0+A
D0–A
D1+A
D1–A
D0+B
D0–B
D1+B
D1–B
FCO+
FCO–
D0+C
D0–C
D1+C
D1–C
D0+D
D0–D
D1+D
D1–D
DCO+
DCO–
Figure 1.
as programmable output clock and data alignment and digital
test pattern generation. The available digital test patterns
include built-in deterministic and pseudorandom patterns, along
with custom user-defined test patterns entered via the serial port
interface (SPI).
The AD9653 is available in a RoHS-compliant, 48-lead LFCSP.
It is specified over the industrial temperature range of −40°C to
+85°C. This product is protected by a U.S. patent.
PRODUCT HIGHLIGHTS
1. Small Footprint.
Four ADCs are contained in a small, space-saving package.
2. Low power of 164 mW/channel at 125 MSPS with scalable
power options.
3. Pin compatible to the AD9253 14-bit quad and the AD9633
12-bit quad ADC.
4. Ease of Use.
A data clock output (DCO) operates at frequencies of up to
500 MHz and supports double data rate (DDR) operation.
5. User Flexibility.
The SPI control offers a wide range of flexible features to
meet specific system requirements.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices foritsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One T echnology Wa y, P .O. Box 91 06, Norwood, MA 02062-9106, U .S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2012 Analog Devices, Inc. All rights reserved.
http://www.Datasheet4U.com
1 page  
Data Sheet
AD9653
AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2.0 V p-p full-scale differential input at −1.0 dBFS; VREF = 1.0 V, DCS off, unless otherwise noted.
Table 3.
Parameter1
Temperature Min Typ Max
SIGNAL-TO-NOISE RATIO (SNR)
fIN = 9.7 MHz
fIN = 15 MHz
fIN = 70 MHz
fIN = 128 MHz
fIN = 200 MHz
SIGNAL-TO-NOISE-AND-DISTORTION RATIO (SINAD)
25°C 78
25°C 77.8
Full 75.5 76.5
25°C 73.9
25°C 71.5
fIN = 9.7 MHz
fIN = 15 MHz
fIN = 70 MHz
fIN = 128 MHz
fIN = 200 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
25°C 78
25°C 77.7
Full 74.6 76.1
25°C 73.6
25°C 70.3
fIN = 9.7 MHz
fIN = 15 MHz
fIN = 70 MHz
fIN = 128 MHz
fIN = 200 MHz
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
25°C 12.7
25°C 12.6
Full 12.1 12.4
25°C 11.9
25°C 11.4
fIN = 9.7 MHz
fIN = 15 MHz
fIN = 70 MHz
fIN = 128 MHz
fIN = 200 MHz
WORST HARMONIC (SECOND OR THIRD)
25°C 96
25°C 93
Full 78 89
25°C 87
25°C 77
fIN = 9.7 MHz
fIN = 15 MHz
fIN = 70 MHz
fIN = 128 MHz
fIN = 200 MHz
WORST OTHER HARMONIC OR SPUR
25°C −98
25°C −93
Full −78 −89
25°C −87
25°C −77
fIN = 9.7 MHz
fIN = 15 MHz
fIN = 70 MHz
fIN = 128 MHz
fIN = 200 MHz
TWO-TONE INTERMODULATION DISTORTION (IMD)—AIN1 AND AIN2 = −7.0 dBFS
25°C
25°C
Full
25°C
25°C
−96
−98
−85 −94
−89
−83
fIN1 = 70.5 MHz, fIN2 = 72.5 MHz
CROSSTALK2
25°C −90
25°C 91
CROSSTALK (OVERRANGE CONDITION)3
25°C 87
POWER SUPPLY REJECTION RATIO (PSRR)4
AVDD
25°C 31
DRVDD
25°C 79
ANALOG INPUT BANDWIDTH, FULL POWER
25°C 650
Unit
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
Bits
Bits
Bits
Bits
Bits
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dB
dB
dB
dB
MHz
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.
2 Crosstalk is measured at 70 MHz with −1.0 dBFS analog input on one channel and no input on the adjacent channel.
3 Overrange condition is defined as the input being 3 dB above full scale.
4 PSRR is measured by injecting a sinusoidal signal at 10 MHz to the power supply pin and measuring the output spur on the FFT. PSRR is calculated as the ratio of the
amplitudes of the spur voltage over the pin voltage, expressed in decibels.
Rev. 0 | Page 5 of 40
5 Page 
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 8.
Parameter
Electrical
AVDD to AGND
DRVDD to AGND
Digital Outputs
(D0±x, D1±x, DCO+, DCO−, FCO+,
FCO−) to AGND
CLK+, CLK− to AGND
VIN+x, VIN−x to AGND
SCLK/DTP, SDIO/OLM, CSB to AGND
SYNC, PDWN to AGND
RBIAS to AGND
VREF, SENSE to AGND
Environmental
Operating Temperature
Range (Ambient, VREF = 1.0 V)
Operating Temperature
Range (Ambient, VREF = 1.3 V)
Maximum Junction
Temperature
Lead Temperature
(Soldering, 10 sec)
Storage Temperature
Range (Ambient)
Rating
−0.3 V to +2.0 V
−0.3 V to +2.0 V
−0.3 V to +2.0 V
−0.3 V to +2.0 V
−0.3 V to +2.0 V
−0.3 V to +2.0 V
−0.3 V to +2.0 V
−0.3 V to +2.0 V
−0.3 V to +2.0 V
−40°C to +85°C
0°C to 85°C
150°C
300°C
−65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
AD9653
THERMAL RESISTANCE
Table 9. Thermal Resistance
Package Type
Air Flow
Velocity
(m/sec)
48-Lead LFCSP 0.0
7 mm × 7 mm 1.0
(CP-48-13)
2.5
θJA1
23.7
20.0
18.7
θJB θJC Unit
7.8 7.1 °C/W
N/A N/A °C/W
N/A N/A °C/W
1 θJA for a 4-layer PCB with solid ground plane (simulated). Exposed pad
soldered to PCB.
ESD CAUTION
Rev. 0 | Page 11 of 40
11 Page | ||
| Páginas | Total 40 Páginas | |
| PDF Descargar | [ Datasheet AD9653.PDF ] | |
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