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PDF AD280 Data sheet ( Hoja de datos )
| Número de pieza | AD280 | |
| Descripción | Universal Multichannel Industrial Signal Conditioning ADC | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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a
Universal Multichannel Industrial
Signal Conditioning ADC
PRELIMINARY TECHNICAL DATA
AD280
FEATURES
Four Input Channels, with Protection and Switchable
Attenuation
Provision for Cold Junction Sensor
Programmable Excitation Sources for RTD Measure-
ment and Open Input Detection
PGA with Programmable Gains from 1 to 128
High Resolution Integrating A/D Converter with Pro-
grammable Integration Period, Up to 18-Bit Usable
Resolution
2.5 Volt Reference
Crystal Oscillator
Charge Pump Circuit to Allow Single +5 V Power
Serial Interface Compatible with Most Microcontrollers
and Microprocessors
APPLICATIONS
Industrial Data Acquisition
DCS (Distributed Control Systems)
PLC (Programmable Logic Controllers)
FUNCTIONAL BLOCK DIAGRAM
DIN0–DIN3
DOUT0–
DOUT3
EXC0
EXC1
EXC2
EXC3
ISET
AIN0
AIN1
AIN2
AIN3
GND SNSE
AGND
CJCIN
REFIN
REFOUT
EXC
CONTROL
LOGIC
SK
DI
DO
CE
DRDY
RESET
INPUT
MUX
PGA
CHARGE
BALANCE
A/D
PTAT
AD280
REF
XTAL
OSC
CHARGE
PUMP
XTAL XTAL2 XTAL1
OUT
CPE
DVDD
AVDD
ALO
CINT1
CINT2
PGAOUT
DGND
C1
C2
C3
GENERAL DESCRIPTION
The AD280 is a front-end integrated circuit for use in industrial
Ydata acquisition applications. It has been specifically designed
Rfor the stringent requirements of industrial applications, with
Afunctions such as protection/protectability and high normal-
INmode rejection. The AD280 can be configured to accept up to
Lfour mV/V/TC inputs, or up to two RTD inputs (in 2-, 3- or 4-
IM Awire connection modes).
L ICThe AD280 is not a stand-alone product, but is intended to be
E Nused with a companion microcontroller or microprocessor.
RDescriptions of appropriate algorithms and control routines for
P CH Athis device are contained in this data sheet, as well as on a
E Tseparate application note.
T AThe four primary input channels are designed for high input
Dimpedance for input signals up to ± 2.5 volts. Each also con-
The AD280 also offers four configurable excitation current
sources. Two of these sources can be configured to provide
excitation for RTDs, the amplitude of which can be set by an
external resistor. All four excitation sources can be set to pro-
vide +25 nA or –25 nA for use in detecting open inputs. The
excitation sources are separately pinned out to allow for external
protection devices to achieve very high normal-mode voltage
protection.
The input multiplexer feeds a programmable gain amplifier,
with binary gains from 1 to 128. The PGA drives a high resolu-
tion integrating A/D converter, which is software programmable
for integration time and can achieve usable resolution of up to
18 bits.
The AD280 features a serial interface, operable to 10 MHz, and
is compatible with a wide variety of microcontrollers and micro-
tains a programmable input attenuator for input ranges up to
processors. An onboard crystal oscillator and charge pump
± 10 volts at reduced input impedance. The inputs contain inter- circuit are provided. The charge pump circuit, requiring just
nal protection to allow for overload without affecting the accu- two external capacitors, provides the negative bias for this de-
racy or operability of adjacent inputs. The input multiplexer
vice and allows full operation from a single +5 V supply.
also features a ground sense input and a separate input (with
programmable excitation) for solid-state or thermistor tempera-
ture sensors for cold junction compensation of thermocouples.
An internal PTAT (Proportional to Absolute Temperature)
Four general purpose digital outputs and four general purpose
digital inputs are also provided; these may be used to implement
external functions that may be required in some applications.
sensor permits measurement of internal die temperature.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1998
http://www.Datasheet4U.com
1 page  
Pin #
1
2
3
4
5
6
7
8, 9, 10, 11
12–15
16
17
18
19
20
21
22, 23
24
25–28
29
30
31
32
33
34–37
38
39, 41
40
42
AD280
PIN FUNCTION DESCRIPTION
Pin Name
Description
CPE
XTALOUT
XTAL1
XTAL2
AVDD
ALO
ISET
EXC0–EXC3
AIN0–AIN3
REFOUT
REFIN
CJCIN
GND SENSE
AGND
PGAOUT
CINT1, CINT2
RESET
DIN3–DIN0
DRDY
DI
DO
CE
SK
DOUT0–DOUT3
C3
C2, C1
DGND
DVDD
Charge Pump Enable. When tied to a Logic “1,” enables the internal charge pump within the
AD280, allowing single supply operation.
Buffered Output from the Crystal Oscillator.
Connection for External Crystal.
Connection for External Crystal.
Positive power supply connection for analog circuit; nominally +5 V ± 5%.
Negative Power Supply Connection; tied externally to C3 (Pin 38) Nominally –5 V ± 5%
supplied externally if charge pump is not used (see Pin 1)
Connection for external resistor, which sets the magnitude of the current used for RTD excitation.
Excitation outputs used to supply open circuit detection current (all four) or RTD excitation
current (EXC0 and EXC1 only).
Analog Input Channels; single-ended inputs with respect to analog ground.
Reference Voltage Output. Nominally +2.5 V.
Reference Voltage Input. Nominally connected to REFOUT.
Cold Junction Compensation Sensor Input. Can be connected to a thermistor or silicon tem-
perature sensor for TC applications.
Ground Sense Input. Used for measuring ground to compensate for ground loops or other
offsets.
YAnalog Ground. All input signals are referenced to this pin.
ROutput of the Programmable Gain Amplifiers;upplied primarily for test and diagnostic purposes.
AConnection for External Integration Capacitor; Nominally 4.7 nF.
IN LReset Input to Internal Logic. When at Logic “0,” forces internal logic into the command mode
IM Acondition. Normally connected to a power-up reset circuit or RC reset circuit.
L ICGeneral purpose digital inputs, accessible via the serial interface.
Data Ready Output. When at Logic “1,” indicates that the most recent A/D conversion is com-
E Nplete and that data is available. This signal is also available via the serial interface, located in the
R Hstatus byte.
P EC TAData Input for the Serial Interface.
T AData Output from the Serial Interface. In a three-state condition unless a data read command is
Dbeing executed.
Chip Enable Input. This signal is used to frame each byte of a command or data transfer.
Shift Clock Input. This signal clocks data to/from the AD280 via the serial interface.
General purpose digital inputs, accessible via the serial interface.
Connection for the shunt capacitor required by the charge pump circuit (nominally 1 ␣ µF/10␣ V
tantalum, low ESR (Effective Series Resistance), negative terminal connected to Pin 38).
Connections for the series capacitor required by the charge pump (nominally 1␣ µF/10 V tanta-
lum, low ESR (Effective Series Resistance), negative terminal connected to Pin 39).
Digital Ground.
Power supply input for digital portion of the AD280. Nominally +5 V ± 5%.
REV. 0
–5–
5 Page 
AD280
CMD:
WRITEABLE REGISTERS
READABLE REGISTERS
MSB
LSB
MSB
LSB
NA
NA
NA
CMD CMD CMD CMD
NA CODE CODE CODE CODE
STATUS: DRDY NA
3210
NA
NA
DIN DIN DIN
32 1
DIN
0
CFG4:
MSB
LSB
EXC3 EXC3 EXC2 EXC2 EXC1 EXC1 EXC0 EXC0
HI LO HI LO HI LO HI LO
MSB
LSB
DATA2:
DATA
MSB
BIT
22
BIT
21
BIT
20
BIT
19
BIT
18
BIT
17
BIT
16
CFG3:
MSB
LSB
CJC
EXC
NA PGA2 PGA1 PGA0 MUX2 MUX1 MUX0
MSB
LSB
DATA1:
BIT BIT BIT BIT
15 14 13 12
BIT
11
BIT BIT BIT
10 9
8
CFG2:
MSB
LSB
ATTEN ATTEN ATTEN ATTEN
CH3 CH2 CH1 CH0
DOUT
3
DOUT
2
DOUT
1
DOUT
0
MSB
LSB
DATA0:
BIT BIT BIT BIT BIT BIT
7 6 5 432
BIT DATA
1 LSB
MSB
LSB
CFG1:
TINT BIT
MSB 14
BIT
13
BIT
12
BIT
11
BIT BIT
10 9
BIT
8
CFG0:
MSB
LSB
BIT BIT BIT BIT BIT BIT BIT TINT
7 6 5 4 3 2 1 LSB
Figure 10. AD280 Internal Registers
YTable III. Command Codes and Corresponding Functions
R␣ ␣ Command Code
ACC3 CC2 CC1 CC0 Function
Parameter
IN L0 0 0 0 NO OPERATION
None
IM A0 0 0 1 READ STATUS
1
L IC0 0 1 0 READ DATA0
1
0 0 1 1 READ DATA1
1
E N0 1 0 0 READ DATA2
1
R H0 1 0 1 READ DATA0/DATA1/DATA2 3
P C A0 1 1 0 NO OPERATION
None
E T0 1 1 1 NO OPERATION
None
T A1 0 0 0 WRITE CFG0
1
D1 0 0 1 WRITE CFG1
1
1 0 1 0 WRITE CFG0/CFG1
2
1.␣ Wait for the conversion to complete.
2. Set the configuration parameters for the next conversion.
3. Wait for settling of the MUX and PGA (1 mS max). Read
the data from the previous conversion while waiting.
4.␣ Trigger the A/D for the next conversion.
All AD280 registers may be read or written in a “single byte”
mode by using the appropriate commands. In the single byte
mode, the command code specifies which individual register is
to be read or written. The byte must be read or written immedi-
ately after the command code is sent to the AD280.
In addition to byte-at-a-time access, “multiple byte” mode
allows certain register combinations to be read or written with-
out the need to transmit a command byte for each register. The
1 0 1 1 WRITE CFG2
1 1 0 0 WRITE CFG3
1
1
command code specifies the number of bytes that follow. Up to
three bytes of data, in ascending order, may be transferred after
1 1 0 1 WRITE CFG4
1 1 1 0 WRITE CFG2/CFG3/CFG4
1
3
the command byte. This capability substantially reduces the
time required to access the AD280, since in most cases the
1 1 1 1 START CONVERSION
None
register groupings will always be read or written together. It is
important to note that in all cases, regardless of whether single
The four “read” registers in the AD280 consist of three data
bytes (DATA0, DATA1, DATA2) and a STATUS byte. The
three data bytes constitute a 24-bit twos-complement binary
or multiple byte mode is used, each byte transferred will require
the complete sequence of the CE (Chip Enable) and SK (Shift
Clock) pins.
integer that is proportional to the signal data. The status byte
contains the auxiliary digital input data, along with an image of
the DRDY signal, which is a copy of the separate external
DRDY line.
The data bytes and status byte may be read at any time. If read
during an A/D conversion, the data bytes will contain the results
of the LAST conversion completed. They will not be updated
with the NEW conversion data until the next conversion is com-
SETTING THE A/D INTEGRATION PERIOD
The integration period of the AD280’s A/D converter is set by
writing to the CONFIG0 and CONFIG1 registers. These two
bytes constitute a 16-bit binary integer which represents the
upper 16 bits of a 21-bit counter clocked by the AD280’s clock.
The formula for the integration period is:
DCONFIG0/1 = (FCLK × TINT)/32
plete. The user is responsible for reading the data when it is
valid. The data is valid after one conversion is complete (i.e.,
where DCONFIG0/1 represents a 16-bit integer. For example, when
using a 10 MHz clock frequency, and when an integration
when DRDY goes high), and remains valid until the next con-
version is complete. The data must be read early enough in the
conversion cycle to assure that it is not updated during the
period o f 16.666 ms is desired, the required integer is 5209 10,
or 145916. Practical integration periods range from 1 ms to
200 ms, depending upon clock speed.
data transfer. Normally, it is most efficient to use the follow-
ing sequence:
REV. 0
–11–
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet AD280.PDF ] | |
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