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PDF ADSP-BF506F Data sheet ( Hoja de datos )
| Número de pieza | ADSP-BF506F | |
| Descripción | Blackfin Embedded Processor | |
| Fabricantes | Analog Devices | |
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Blackfin
Embedded Processor
ADSP-BF504/ADSP-BF504F/ADSP-BF506F
FEATURES
Up to 400 MHz high performance Blackfin processor
Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs,
40-bit shifter
RISC-like register and instruction model for ease of
programming and compiler-friendly support
Advanced debug, trace, and performance monitoring
Accepts a range of supply voltages for internal and I/O opera-
tions. See Operating Conditions on Page 26
Internal 32M bit flash (available on ADSP-BF504F and
ADSP-BF506F processors)
Internal ADC (available on ADSP-BF506F processor)
Off-chip voltage regulator interface
88-lead (12 mm × 12 mm) LFCSP package for ADSP-BF504
and ADSP-BF504F processors
120-lead (14 mm × 14 mm) LQFP package for ADSP-BF506F
processor
MEMORY
68K bytes of L1 SRAM (processor core-accessible) memory
(See Table 1 on Page 3 for L1 and L3 memory size details)
External (interface-accessible) memory controller with glue-
less support for internal 32M bit flash and boot ROM
Flexible booting options from internal flash and SPI memory
or from host devices including SPI, PPI, and UART
Memory management unit providing memory protection
PERIPHERALS
Two 32-bit up/down counters with rotary support
Eight 32-bit timers/counters with PWM support
Two 3-phase 16-bit center-based PWM units
2 dual-channel, full-duplex synchronous serial ports
(SPORTs), supporting eight stereo I2S channels
2 serial peripheral interface (SPI) compatible ports
2 UARTs with IrDA support
Parallel peripheral interface (PPI), supporting ITU-R 656
video data formats
Removable storage interface (RSI) controller for MMC, SD,
SDIO, and CE-ATA
Internal ADC with 12 channels, 12 bits, and up to 2 MSPS
ADC controller module (ACM), providing a glueless interface
between Blackfin processor and internal or external ADC
Controller Area Network (CAN) controller
2-wire interface (TWI) controller
12 peripheral DMAs
2 memory-to-memory DMA channels
Event handler with 52 interrupt inputs
35 general-purpose I/Os (GPIOs), with programmable
hysteresis
Debug/JTAG interface
On-chip PLL capable of frequency multiplication
WATCHDOG TIMER
VOLTAGE REGULATOR INTERFACE
B
JTAG TEST AND EMULATION
PERIPHERAL
ACCESS BUS
INTERRUPT
CONTROLLER
L1 INSTRUCTION
MEMORY
EAB
16
32M BIT
FLASH
L1 DATA
MEMORY
DMA
CONTROLLER
DCB
DMA
ACCESS
BUS
DEB
MEMORY PORT
FLASH CONTROL
BOOT
ROM
COUNTER1–0
TIMER7–0
PWM 1–0
SPORT1–0
SPI1–0
UART1–0
PPI
RSI
ACM
CAN
TWI
GPIO
PORT F
PORT G
PORT H
ADC
Figure 1. Processor Block Diagram
Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.
Rev. B
Document Feedback
Information furn ished by An alog D evices is believed t o be ac curate and reli able.
However, no r esponsibility is assumed by Analo g Dev ices for its use, n or fo r any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or p atent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: 781.329.4700
©2014 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
http://www.Datasheet4U.com
1 page  
ADSP-BF504/ADSP-BF504F/ADSP-BF506F
Blackfin processors support a modified Harvard architecture in
combination with a hierarchical memory structure. Level 1 (L1)
memories are those that typically operate at the full processor
speed with little or no latency. At the L1 level, the instruction
memory holds instructions only. The data memory holds data,
and a dedicated scratchpad data memory stores stack and local
variable information.
In addition, multiple L1 memory blocks are provided, offering a
configurable mix of SRAM and cache. The memory manage-
ment unit (MMU) provides memory protection for individual
tasks that may be operating on the core and can protect system
registers from unintended access.
The architecture provides three modes of operation: user mode,
supervisor mode, and emulation mode. User mode has
restricted access to certain system resources, thus providing a
protected software environment, while supervisor mode has
unrestricted access to the system and core resources.
The Blackfin processor instruction set has been optimized so
that 16-bit opcodes represent the most frequently used instruc-
tions, resulting in excellent compiled code density. Complex
DSP instructions are encoded into 32-bit opcodes, representing
fully featured multifunction instructions. Blackfin processors
support a limited multi-issue capability, where a 32-bit instruc-
tion can be issued in parallel with two 16-bit instructions,
allowing the programmer to use many of the core resources in a
single instruction cycle.
The Blackfin processor assembly language uses an algebraic syn-
tax for ease of coding and readability. The architecture has been
optimized for use in conjunction with the C/C++ compiler,
resulting in fast and efficient software implementations.
MEMORY ARCHITECTURE
The Blackfin processor views memory as a single unified
4G byte address space, using 32-bit addresses. All resources,
including internal memory, external memory, and I/O control
registers, occupy separate sections of this common address
space. The memory portions of this address space are arranged
in a hierarchical structure to provide a good cost/performance
balance of some very fast, low latency core-accessible memory
as cache or SRAM and to provide larger, lower cost and perfor-
mance interface-accessible memory systems. See Figure 3.
The core-accessible L1 memory system is the highest perfor-
mance memory available to the Blackfin processor. The
interface-accessible memory system, accessed through the
external bus interface unit (EBIU), provides access to the inter-
nal flash memory and boot ROM.
The memory DMA controller provides high bandwidth data
movement capability. It can perform block transfers of code
or data between the internal memory and the external
memory spaces.
Internal (Core-Accessible) Memory
The processor has three blocks of core-accessible memory,
providing high-bandwidth access to the core.
The first block is the L1 instruction memory, consisting of
32K bytes SRAM, of which 16K bytes can be configured as a
four-way set-associative cache. This memory is accessed at full
processor speed.
The second core-accessible memory block is the L1 data mem-
ory, consisting of 32K bytes of SRAM, of which 16K bytes may
be configured as cache. This memory block is accessed at full
processor speed.
The third memory block is 4K bytes of scratchpad SRAM, which
runs at the same speed as the L1 memories, but this memory is
only accessible as data SRAM and cannot be configured as cache
memory.
0xFFFF FFFF
0xFFE0 0000
0xFFC0 0000
0xFFB0 1000
0xFFB0 0000
0xFFA1 4000
0xFFA0 8000
0xFFA0 4000
0xFFA0 0000
0xFF80 8000
0xFF80 4000
0xFF80 0000
0xEF00 1000
0xEF00 0000
0x2040 0000
0x2000 0000
0x0000 0000
CORE MEMORY MAPPED REGISTERS
SYSTEM MEMORY MAPPED REGISTERS
RESERVED
INTERNAL SCRATCHPAD RAM (4K BYTES)
RESERVED
RESERVED
L1 INSTRUCTION SRAM/CACHE (16K BYTES)
L1 INSTRUCTION BANK A SRAM (16K BYTES)
RESERVED
L1 DATA BANK A SRAM/CACHE (16K BYTES)
L1 DATA BANK A SRAM (16K BYTES)
RESERVED
BOOT ROM (4K BYTES)
RESERVED
SYNC FLASH (32M BITS) *
RESERVED
* AVAILABLE ON PARTS WITH SYNC FLASH (F)
Figure 3. Internal/External Memory Map
External (Interface-Accessible) Memory
External memory is accessed via the EBIU memory port. This
16-bit interface provides a glueless connection to the internal
flash memory and boot ROM. Internal flash memory ships from
the factory in an erased state except for Block 0 of the parameter
bank. Block 0 of the Flash memory parameter bank ships from
the factory in an unknown state. An erase operation should be
performed prior to programming this block.
I/O Memory Space
The processor does not define a separate I/O space. All
resources are mapped through the flat 32-bit address space.
On-chip I/O devices have their control registers mapped into
memory-mapped registers (MMRs) at addresses near the top of
the 4G byte address space. These are separated into two smaller
blocks. One contains the control MMRs for all core functions,
and the other contains the registers needed for setup and con-
trol of the on-chip peripherals outside of the core. The MMRs
are accessible only in supervisor and emulation modes and
appear as reserved space to on-chip peripherals.
Rev. B | Page 5 of 84 | April 2014
5 Page 
ADSP-BF504/ADSP-BF504F/ADSP-BF506F
• DMA operations with single-cycle overhead—Each SPORT
can automatically receive and transmit multiple buffers of
memory data. The processor can link or chain sequences of
DMA transfers between a SPORT and memory.
• Interrupts—Each transmit and receive port generates an
interrupt upon completing the transfer of a data word or
after transferring an entire data buffer, or buffers,
through DMA.
• Multichannel capability—Each SPORT supports 128 chan-
nels out of a 1024-channel window and is compatible with
the H.100, H.110, MVIP-90, and HMVIP standards.
SERIAL PERIPHERAL INTERFACE (SPI) PORTS
The ADSP-BF50x processors have two SPI-compatible ports
that enable the processor to communicate with multiple SPI-
compatible devices.
The SPI interface uses three pins for transferring data: two data
pins MOSI (Master Output-Slave Input) and MISO (Master
Input-Slave Output) and a clock pin, serial clock (SCK). An SPI
chip select input pin (SPIx_SS) lets other SPI devices select the
processor, and three SPI chip select output pins (SPIx_SEL3–1)
let the processor select other SPI devices. The SPI select pins are
reconfigured general-purpose I/O pins. Using these pins, the
SPI port provides a full-duplex, synchronous serial interface,
which supports both master/slave modes and multimaster
environments.
The SPI port’s baud rate and clock phase/polarities are
programmable, and it has an integrated DMA channel,
configurable to support transmit or receive data streams. The
SPI’s DMA channel can only service unidirectional accesses at
any given time.
The SPI port’s clock rate is calculated as:
SPI Clock Rate
=
----------f--S--C---L---K-----------
2 SPI_BAUD
Where the 16-bit SPI_BAUD register contains a value of 2
to 65,535.
During transfers, the SPI port simultaneously transmits and
receives by serially shifting data in and out on its two serial data
lines. The serial clock line synchronizes the shifting and sam-
pling of data on the two serial data lines.
UART PORTS (UARTS)
The ADSP-BF50x Blackfin processors provide two full-duplex
universal asynchronous receiver/transmitter (UART) ports.
Each UART port provides a simplified UART interface to other
peripherals or hosts, enabling full-duplex, DMA-supported,
asynchronous transfers of serial data. A UART port includes
support for five to eight data bits; one or two stop bits; and
none, even, or odd parity. Each UART port supports two modes
of operation:
• PIO (programmed I/O). The processor sends or receives
data by writing or reading I/O-mapped UART registers.
The data is double-buffered on both transmit and receive.
• DMA (direct memory access). The DMA controller trans-
fers both transmit and receive data. This reduces the
number and frequency of interrupts required to transfer
data to and from memory. Each UART has two dedicated
DMA channels, one for transmit and one for receive. These
DMA channels have lower default priority than most DMA
channels because of their relatively low service rates. Flexi-
ble interrupt timing options are available on the transmit
side.
Each UART port’s baud rate, serial data format, error code gen-
eration and status, and interrupts are programmable:
• Supporting bit rates ranging from (fSCLK/1,048,576) to
(fSCLK) bits per second.
• Supporting data formats from 7 to 12 bits per frame.
• Both transmit and receive operations can be configured to
generate maskable interrupts to the processor.
The UART port’s clock rate is calculated as
UART Clock Rate = 1--6-----1---E-–-----D----B-O-----f-S---C---UL---K-A----R----T---_---D----iv---i-s--o---r--
Where the 16-bit UART divisor comes from the UARTx_DLH
register (most significant 8 bits) and UARTx_DLL register (least
significant eight bits), and the EDBO is a bit in the
UARTx_GCTL register.
In conjunction with the general-purpose timer functions, auto-
baud detection is supported.
The UARTs feature a pair of UAx_RTS (request to send) and
UAx_CTS (clear to send) signals for hardware flow purposes.
The transmitter hardware is automatically prevented from
sending further data when the UAx_CTS input is de-asserted.
The receiver can automatically de-assert its UAx_RTS output
when the enhanced receive FIFO exceeds a certain high-water
level. The capabilities of the UARTs are further extended with
support for the Infrared Data Association (IrDA®) Serial Infra-
red Physical Layer Link Specification (SIR) protocol.
PARALLEL PERIPHERAL INTERFACE (PPI)
The processor provides a parallel peripheral interface (PPI) that
can connect directly to parallel A/D and D/A converters, video
encoders and decoders, and other general-purpose peripherals.
The PPI consists of a dedicated input clock pin, up to three
frame synchronization pins, and up to 16 data pins. The input
clock supports parallel data ratesup to half the system clock rate
and the synchronization signals can be configured as either
inputs or outputs.
Rev. B | Page 11 of 84 | April 2014
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ADSP-BF506F.PDF ] | |
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