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PDF ADF4155 Data sheet ( Hoja de datos )
| Número de pieza | ADF4155 | |
| Descripción | Integer-N/Fractional-N PLL Synthesizer | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Data Sheet
Integer-N/Fractional-N PLL Synthesizer
ADF4155
FEATURES
GENERAL DESCRIPTION
Input frequency range: 500 MHz to 8000 MHz
The ADF4155 allows implementation of fractional-N or
Fractional-N synthesizer and integer-N synthesizer
integer-N phase-locked loop (PLL) frequency synthesizers
Phase frequency detector (PFD) up to 125 MHz
when used with an external loop filter, external voltage
High resolution 38-bit modulus
controlled oscillator (VCO), and external reference frequency.
Separate charge pump supply (VP) allows extended tuning
voltage in 5 V systems
Programmable divide by 1, 2, 4, 8, 16, 32, or 64 output
Differential and single-ended reference inputs
Power supply: 3.3 V ± 5%
Logic compatibility: 1.8 V
Programmable dual-modulus prescaler (P) of 4/5 or 8/9
The ADF4155 is for use with external VCO parts up to an
8 GHz operating frequency. The high resolution programmable
modulus allows synthesis of exact frequencies with 0 Hz error.
The VCO frequency can be divided by 1, 2, 4, 8, 16, 32, or 64 to
allow the user to generate RF output frequencies as low as
7.8125 MHz.
Programmable output power level
3-wire serial interface
Analog and digital lock detect
Control of all on-chip registers is through a simple 3-wire
interface. The device operates with a nominal power supply of
3.3 V ± 5% and can be powered down when not in use.
APPLICATIONS
The ADF4155 is available in a 24-lead, 4 mm × 4 mm LFCSP
Wireless infrastructure (W-CDMA, TD-SCDMA, WiMAX, GSM,
package.
PCS, DCS, DECT)
Point to point/point to multipoint microwave links
Test equipment
Wireless LANs, CATV equipment
Clock generation
FUNCTIONAL BLOCK DIAGRAM
AVDD
DVDD
VP
RFVDD
RSET
REFIN+
REFIN –
CLK
DATA
LE
CE
×2
DOUBLER
10-BIT R
COUNTER
÷2
DIVIDER
DATA REGISTER
FUNCTION
LATCH
INTEGER FRACTION MODULUS
REG
REG
REG
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
N COUNTER
LOCK
DETECT
MULTIPLEXER
CHARGE
PUMP
PHASE
COMPARATOR
ADF4155
÷ 1/2/4/8/16/32/64
MUXOUT
CPOUT
CREG1
CREG2
OUTPUT
STAGE
RFOUT +
RFOUT –
PDBRF
INPUT
STAGE
RFIN +
RFIN–
AGND
DGND
CPGND
Figure 1.
RFGND
Rev. 0
Document Feedback
Information furnished by Analog D evices is believedto be accurate and reliable. However, n o
responsibilityis assumedby Analog Devicesfor itsuse, nor for any infringementsof patents or other
rightsofthirdparties thatmay resultfrom its use.Specificationssubject tochangewithout notice.No
license is grantedby implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks are ht e propertyof their respective owners.
One T echnology Wa y, P .O. Box 9 106, Norwood, M A 02 062-9106, U .S.A.
Tel: 781.329.4700
©2014 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
http://www.Datasheet4U.com
1 page  
Data Sheet
ADF4155
TIMING CHARACTERISTICS
AVDD = DVDD = RFVDD = 3.3 V ± 5%, AVDD ≤ VP ≤ 5.5V, AGND = DGND = RFGND = CPGND = 0 V, 1.8 V and 3 V logic levels used, and TA =
TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
t1
t2
t3
t4
t5
t6
t7
Limit
20
10
10
25
25
10
20
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Description
LE setup time
DATA to CLK setup time
DATA to CLK hold time
CLK high duration
CLK low duration
CLK to LE setup time
LE pulse width
Timing Diagram
CLK
DATA
DB31 (MSB)
t4 t5
t2 t3
DB30
DB3
(CONTROL BIT C4)
DB2
(CONTROL BIT C3)
DB1
(CONTROL BIT C2)
LE
t1
Figure 2. Timing Diagram
DB0 (LSB)
(CONTROL BIT C1)
t7
t6
Rev. 0 | Page 5 of 32
5 Page 
Data Sheet
–80
–90
–100
–110
–120
–130
–140
–150
–160
1k
10k 100k 1M 10M
FREQUENCY OFFSET (Hz)
Figure 16. RF Output Phase Noise, RF Divider = 2 Enabled, Fractional-N,
RFOUT+ = 2900 MHz, REFIN+/REFIN− = 122.88 MHz, fPFD = 61.44 MHz,
Loop Filter Bandwidth = 60 kHz
ADF4155
Rev. 0 | Page 11 of 32
11 Page | ||
| Páginas | Total 32 Páginas | |
| PDF Descargar | [ Datasheet ADF4155.PDF ] | |
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