PDF AGLN060 Data sheet ( Hoja de datos )

Número de pieza	AGLN060
Descripción	IGLOO nano Low Power Flash FPGAs
Fabricantes	Microsemi
Logotipo
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IGLOO nano Low Power Flash FPGAs with FlashFreeze Technology Revision 14 Features and Benefits Low Power • nanoPower Consumption—Industry’s Lowest Power • 1.2 V to 1.5 V Core Voltage Support for Low Power • Supports Single-Voltage System Operation • Low Power Active FPGA Operation • FlashFreeze Technology Enables Ultra-Low Power Consumption while Maintaining FPGA Content • Easy Entry to / Exit fromUltra-Low Power FlashFreeze Mode Small Footprint Packages • As Small as 3x3 mm in Size Wide Range of Features • 10,000 to 250,000 System Gates • Up to 36 kbits of True Dual-Port SRAM • Up to 71 User I/Os Reprogrammable Flash Technology • 130-nm, 7-Layer Metal, Flash-Based CMOS Process • Live-at-Power-Up (LAPU) Level 0 Support • Single-Chip Solution • Retains Programmed Design When Powered Off • 250 MHz (1.5 V systems) and 160 MHz (1.2 V systems) System Performance In-System Programming (ISP) and Security • ISP Using On -Chip 128 -Bit Advanced Enc ryption S tandard • F(AlaEsSh)LDocekc®ryDpteiosingnveiadJtToASGec(IuErEeEFP15G3A2–Ccoonmtepnlitasnt) •1 .2 V Programming High-Performance Routing Hierarchy • Segmented, Hierarchical Routing and Clock Structure Advanced I/Os • 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation • Bank-Selectable I/O Voltages—up to 4 Banks per Chip • Single-Ended I/O Standards: LVTTL, LVCMOS 3.3V /2 .5 V / 1.8V /1 .5 V/1 .2 V • Wide Range Po wer Su pply V oltage Sup port per J ESD8-B, Allowing I/Os to Operate from 2.7 V to 3.6 V • Wide Ran ge Power Supp ly V oltage Sup port per JESD8-1 2, Allowing I/Os to Operate from 1.14 V to 1.575 V • I/O Registers on Input, Output, and Enable Paths • Selectable Schmitt Trigger Inputs • Hot-Swappable and Cold-Sparing I/Os • Programmable Output Slew Rate and Drive Strength • Weak Pull-Up/-Down • • IPEinE-ECo11m4p9a.t1ib(lJeTPAaGc)kBagoeusndaacrryosSscathneTIeGsLtOO® Family Clock Conditioning Circuit (CCC) and PLL† • Up to Six CCC Blocks, One with an Integrated PLL • Configurable Phas e Shift, Multiply/Divide, De lay Capabilities, and External Feedback • Wide Input Frequency Range (1.5 MHz up to 250 MHz) Embedded Memory • 1 kbit of FlashROM User Nonvolatile Memory • SRAMs a nd F IFOs wi th Variable-Aspect-Ratio 4 ,608-Bit RAM Blocks (×1, ×2, ×4, ×9, and ×18 organizations)† • True Dual-Port SRAM (except × 18 organization)† Enhanced Commercial Temperature Range • –20°C to +70°C IGLOO nano Devices IGLOO nano-Z Devices1 AGLN010 AGLN0151 AGLN020 AGLN060 AGLN125 AGLN250 AGLN030Z1 AGLN060Z1 AGLN125Z1 AGLN250Z1 System Gates 10,000 15,000 20,000 30,000 60,000 125,000 250,000 Typical Equivalent Macrocells 86 128 172 256 512 1,024 2,048 VersaTiles (D-flip-flops) 260 384 520 768 1,536 3,072 6,144 FlashFreeze Mode (typical, µW) 244 5 10 16 24 RAM Kbits (1,024 bits)2 ––– – 18 36 36 4,608-Bit Blocks2 ––– – 488 FlashROM Kbits (1,024 bits) Secure (AES) ISP2 Integrated PLL in CCCs 2,3 111 1 111 – – – – Yes Yes Yes ––– – 111 VersaNet Globals 444 6 18 18 18 I/O Banks 233 2 224 Maximum User I/Os (packaged device) 34 49 52 77 71 71 68 Maximum User I/Os (Known Good Die) 34 – 52 83 71 71 68 Package Pins UC/CS QFN VQFP UC36 QN48 QN68 UC81, CS81 QN68 UC81, CS81 QN48, QN68 VQ100 CS81 VQ100 CS81 VQ100 CS81 VQ100 Notes: 1. Not recommended for new designs. 2. AGLN030 and smaller devices do not support this feature. 3. AGLN060, AGLN125, and AGLN250 in the CS81 package do not support PLLs. 4. For higher densities and support of additional features, refer to the IGLOO and IGLOOe datasheets. † AGLN030 and smaller devices do not support this feature. September 2012 © 2012 Microsemi Corporation I http://www.Datasheet4U.com 1 page IGLOO nano Low Power Flash FPGAs Table of Contents IGLOO nano Device Overview General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 IGLOO nano DC and Switching Characteristics General Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Calculating Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 User I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 VersaTile Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-57 Global Resource Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-63 Clock Conditioning Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-70 Embedded SRAM and FIFO Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-73 Embedded FlashROM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-87 JTAG 1532 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-88 Pin Descriptions Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 User Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 JTAG Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 Special Function Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 Package Pin Assignments UC36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 UC81 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 CS81 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 QN48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15 QN68 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18 VQ100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-22 Datasheet Information List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8 Safety Critical, Life Support, and High-Reliability Applications Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8 Revision 14 V 5 Page IGLOO nano Low Power Flash FPGAs . Bank 0 CCC RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block I/Os VersaTile ISP AES Decryption User Nonvolatile FlashRom FlashFreeze Technology Charge Pumps Bank 1 Figure 1-3 • IGLOO Device Architecture Overview with Two I/O Banks (AGLN060, AGLN125) Bank 0 CCC RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block I/Os VersaTile ISP AES Decryption User Nonvolatile FlashRom FlashFreeze Technology Charge Pumps Bank 2 Figure 1-4 • IGLOO Device Architecture Overview with Four I/O Banks (AGLN250) Revision 14 1-5 11 Page

Páginas	Total 30 Páginas
PDF Descargar	[ Datasheet AGLN060.PDF ]

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