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AGLN010 Schematic ( PDF Datasheet ) - Microsemi

Teilenummer AGLN010
Beschreibung IGLOO nano Low Power Flash FPGAs
Hersteller Microsemi
Logo Microsemi Logo 




Gesamt 30 Seiten
AGLN010 Datasheet, Funktion
IGLOO nano Low Power Flash FPGAs
with Flash*Freeze Technology
Revision 14
Features and Benefits
Low Power
• nanoPower Consumption—Industry’s Lowest Power
• 1.2 V to 1.5 V Core Voltage Support for Low Power
• Supports Single-Voltage System Operation
• Low Power Active FPGA Operation
• Flash*Freeze Technology Enables Ultra-Low Power
Consumption while Maintaining FPGA Content
• Easy Entry to / Exit fromUltra-Low Power Flash*Freeze Mode
Small Footprint Packages
• As Small as 3x3 mm in Size
Wide Range of Features
• 10,000 to 250,000 System Gates
• Up to 36 kbits of True Dual-Port SRAM
• Up to 71 User I/Os
Reprogrammable Flash Technology
• 130-nm, 7-Layer Metal, Flash-Based CMOS Process
• Live-at-Power-Up (LAPU) Level 0 Support
• Single-Chip Solution
• Retains Programmed Design When Powered Off
• 250 MHz (1.5 V systems) and 160 MHz (1.2 V systems) System
Performance
In-System Programming (ISP) and Security
• ISP Using On -Chip 128 -Bit Advanced Enc ryption S tandard
• F(AlaEsSh)LDocekc®ryDpteiosingnveiadJtToASGec(IuErEeEFP15G3A2–Ccoonmtepnlitasnt)
•1 .2 V Programming
High-Performance Routing Hierarchy
• Segmented, Hierarchical Routing and Clock Structure
Advanced I/Os
• 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
• Bank-Selectable I/O Voltages—up to 4 Banks per Chip
• Single-Ended I/O Standards: LVTTL, LVCMOS
3.3V /2 .5 V / 1.8V /1 .5 V/1 .2 V
• Wide Range Po wer Su pply V oltage Sup port per J ESD8-B,
Allowing I/Os to Operate from 2.7 V to 3.6 V
• Wide Ran ge Power Supp ly V oltage Sup port per JESD8-1 2,
Allowing I/Os to Operate from 1.14 V to 1.575 V
• I/O Registers on Input, Output, and Enable Paths
• Selectable Schmitt Trigger Inputs
• Hot-Swappable and Cold-Sparing I/Os
• Programmable Output Slew Rate and Drive Strength
• Weak Pull-Up/-Down
IPEinE-ECo11m4p9a.t1ib(lJeTPAaGc)kBagoeusndaacrryosSscathneTIeGsLtOO® Family
Clock Conditioning Circuit (CCC) and PLL
• Up to Six CCC Blocks, One with an Integrated PLL
• Configurable Phas e Shift, Multiply/Divide, De lay
Capabilities, and External Feedback
• Wide Input Frequency Range (1.5 MHz up to 250 MHz)
Embedded Memory
• 1 kbit of FlashROM User Nonvolatile Memory
• SRAMs a nd F IFOs wi th Variable-Aspect-Ratio 4 ,608-Bit RAM
Blocks (×1, ×2, ×4, ×9, and ×18 organizations)
• True Dual-Port SRAM (except × 18 organization)
Enhanced Commercial Temperature Range
• –20°C to +70°C
IGLOO nano Devices
IGLOO nano-Z Devices1
AGLN010 AGLN0151 AGLN020
AGLN060 AGLN125 AGLN250
AGLN030Z1 AGLN060Z1 AGLN125Z1 AGLN250Z1
System Gates
10,000
15,000
20,000
30,000
60,000
125,000
250,000
Typical Equivalent Macrocells
86 128 172
256
512
1,024
2,048
VersaTiles (D-flip-flops)
260 384 520
768
1,536
3,072
6,144
Flash*Freeze Mode (typical, µW)
244
5
10 16 24
RAM Kbits (1,024 bits)2
–––
18 36 36
4,608-Bit Blocks2
–––
488
FlashROM Kbits (1,024 bits)
Secure (AES) ISP2
Integrated PLL in CCCs 2,3
111
1
111
– – – – Yes Yes Yes
–––
111
VersaNet Globals
444
6
18 18 18
I/O Banks
233
2
224
Maximum User I/Os (packaged device)
34
49
52
77
71 71 68
Maximum User I/Os (Known Good Die)
34
52
83
71 71 68
Package Pins
UC/CS
QFN
VQFP
UC36
QN48
QN68
UC81,
CS81
QN68
UC81, CS81
QN48, QN68
VQ100
CS81
VQ100
CS81
VQ100
CS81
VQ100
Notes:
1. Not recommended for new designs.
2. AGLN030 and smaller devices do not support this feature.
3. AGLN060, AGLN125, and AGLN250 in the CS81 package do not support PLLs.
4. For higher densities and support of additional features, refer to the IGLOO and IGLOOe datasheets.
† AGLN030 and smaller devices do not support this feature.
September 2012
© 2012 Microsemi Corporation
I
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AGLN010 Datasheet, Funktion

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AGLN010 pdf, datenblatt
IGLOO nano Device Overview
Flash*Freeze Technology
The IGLOO nano device has an ultra-low power static mode, called Flash*Freeze mode, which retains all
SRAM and register information and can still quickly return to normal operation. Flash*Freeze technology
enables the user to quickly (withi n 1 µ s) enter and exit Fla sh*Freeze mode by acti vating the
Flash*Freeze pin while all power supplies are kept at their original values. I/Os, gl obal I/Os, and clocks
can still be driven and can be toggling without impact on power consumption, and the device retains all
core registers, SRAM information, and I/O states. I/Os can be individually configured to either ho ld their
previous state or be tristated during Flash*Freeze mode.
Alternatively, I/Os can be se t to a sp ecific st ate u sing we ak pul l-up or pull-down I/O attri bute
configuration. No po wer is cons umed by the I/O ba nks, clo cks, JTAG pins, or PLL, and the de vice
consumes as little as 2 µW in this mode.
Flash*Freeze technology allows the user to switch to Active mode on demand, thus simplifying the power
management of the device.
The Flash*Freeze pin (active low) can be routed internally to the core to allow the user's logic to decide
when i t is safe to transitio n to this mod e. Refer to Figure 1-5 for a n i llustration of e ntering/exiting
Flash*Freeze mode. It is also possible to use the Flash*Freeze pin as a regular I/O if Flash*Freeze mode
usage is not planned.
Flash*Freeze
Mode Control
IGLOO nano
FPGA
Flash*Freeze Pin
Figure 1-5 • IGLOO nano Flash*Freeze Mode
VersaTiles
The IGLOO nano core consists of VersaTiles, which have been enhanced beyond the ProASICPLUS®
core tiles. The IGLOO nano VersaTile supports the following:
• All 3-input logic functions—LUT-3 equivalent
• Latch with clear or set
• D-flip-flop with clear or set
• Enable D-flip-flop with clear or set
Refer to Figure 1-6 for VersaTile configurations.
LUT-3 Equivalent
X1
X2 LUT-3 Y
X3
D-Flip-Flop with Clear or Set
Data
CLK
CLR
D-FF
Y
Figure 1-6 • VersaTile Configurations
Enable D-Flip-Flop with Clear or Set
Data
CLK
Enable
CLR
D-FF
Y
1-6 Revision 14

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