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GD25Q64B Schematic ( PDF Datasheet ) - ELM

Teilenummer GD25Q64B
Beschreibung Uniform sector dual and quad serial flash
Hersteller ELM
Logo ELM Logo 




Gesamt 44 Seiten
GD25Q64B Datasheet, Funktion
GGDD2255QQ6644BB
DDAATTAASSHHEEEETT
44 - 1
Rev.1.1
http://www.Datasheet4U.com






GD25Q64B Datasheet, Funktion
GD25Q64BxIGx Uniform sector dual and quad serial flash
Uniform Sector
Dual and Quad Serial Flash
GD25Q64B
BLOCK DIAGRAM
WP#(IO2)
Write Control
Logic
HOLD#(IO3)
SCLK
CS#
SI(IO0)
SO(IO1)
SPI
Command &
Control Logic
Status
Register
High Voltage
Generators
Flash
Memory
Page Address
Latch/Counter
Column Decode And
256-Byte Page Buffer
Byte Address
Latch/Counter
464 - 6
Rev.1.1

6 Page









GD25Q64B pdf, datenblatt
GD25Q64BxIGx Uniform sector dual and quad serial flash
Uniform Sector
Dual and Quad Serial Flash
GD25Q64B
QE bit.
The Quad Enable (QE) bit is a non-volatile Read/Write bit in the Status Register that allows Quad operation. When
the QE bit is set to 0 (Default) the WP# pin and HOLD# pin are enable. When the QE pin is set to 1, the Quad IO2 and IO3
pins are enabled. (The QE bit should never be set to 1 during standard SPI or Dual SPI operation if the WP# or HOLD#
pins are tied directly to the power supply or ground)
LB bit.
The LB bit is a non-volatile One Time Program (OTP) bit in Status Register (S10) that provide the write protect control
and status to the Security Registers. The default state of LB is 0, the security registers are unlocked. LB can be set to 1
individually using the Write Register instruction. LB is One Time Programmable, once it’s set to 1, the Security Registers
will become read-only permanently.
CMP bit
The CMP bit is a non-volatile Read/Write bit in the Status Register (S14). It is used in conjunction the BP4-BP0 bits to
provide more flexibility for the array protection. Please see the Status registers Memory Protection table for details. The
default setting is CMP=0.
SUS bit
The SUS bit is a read only bit in the status register (S15 ) that is set to 1 after executing an Erase/Program Suspend
(75H) command. The SUS bit is cleared to 0 by Erase/Program Resume (7AH) command as well as a power-down,
power-up cycle.
Uniform Sector
Dual and Quad Serial Flash
GD25Q64B
7. COMMANDS DESCRIPTION
All commands, addresses and data are shifted in and out of the device, beginning with the most significant bit on the
first rising edge of SCLK after CS# is driven low. Then, the one-byte command code must be shifted in to the device, most
significant bit first on SI, each bit being latched on the rising edges of SCLK.
See Table2, every command sequence starts with a one-byte command code. Depending on the command, this
might be followed by address bytes, or by data bytes, or by both or none. CS# must be driven high after the last bit of the
command sequence has been shifted in. For the command of Read, Fast Read, Read Status Register or Release from
Deep Power-Down, and Read Device ID, the shifted-in command sequence is followed by a data-out sequence. CS# can
be driven high after any bit of the data-out sequence is being shifted out.
For the command of Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Write Enable,
Write Disable or Deep Power-Down command, CS# must be driven high exactly at a byte boundary, otherwise the
command is rejected, and is not executed. That is CS# must driven high when the number of clock pulses after CS# being
driven low is an exact multiple of eight. For Page Program, if at any time the input byte is not a full byte, nothing will happen
and WEL will not be reset.
Table2. Commands
Command Name
Write Enable
Write Disable
Read Status Register
Read Status Register-1
Write Status Register
Read Data
Fast Read
Dual Output
Fast Read
Dual I/O
Fast Read
Quad Output
Fast Read
Byte 1
06H
04H
05H
35H
01H
03H
0BH
3BH
BBH
6BH
Byte 2
Byte 3
Byte 4
Byte 5
(S7-S0)
(S15-S8)
(S7-S0)
A23-A16
A23-A16
A23-A16
A23-A8(2)
A23-A16
(S15-S8)
A15-A8
A15-A8
A15-A8
A7-A0
A7-A0
A7-A0
A7-A40412 - 12(D7-D0)(1)
M7-M0(2)
A15-A8
A7-A0
(D7-D0)
dummy
dummy
dummy
(5) (3)
Byte 6
n-Bytes
(continuous)
(continuous)
(Next byte)
(D7-D0)
(D7-D0)(1)
(continuous)
(continuous)
(continuous)
Rev.1.1
(continuous)
(D7-D0)(3) (continuous)

12 Page





SeitenGesamt 44 Seiten
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