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ADP2323 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADP2323
Beschreibung 20 V Synchronous Step-Down Regulator
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
ADP2323 Datasheet, Funktion
Data Sheet
Dual 3 A, 20 V Synchronous Step-Down
Regulator with Integrated High-Side MOSFET
ADP2323
FEATURES
Input voltage: 4.5 V to 20 V
±1% output accuracy
Integrated 90 mΩ typical high-side MOSFET
Flexible output configuration
Dual output: 3 A/3 A
Parallel single output: 6 A
Programmable switching frequency: 250 kHz to 1.2 MHz
External synchronization input with programmable phase
shift, or internal clock output
Selectable PWM or PFM mode operation
Adjustable current limit for small inductor
External compensation and soft start
Startup into precharged output
Supported by ADIsimPower™ design tool
APPLICATIONS
Communications infrastructure
Networking and servers
Industrial and instrumentation
Healthcare and medical
Intermediate power rail conversion
DC-to-dc point of load applications
GENERAL DESCRIPTION
The ADP2323 is a full featured, dual output, step-down dc-to-
dc regulator based on current-mode architecture. The ADP2323
integrates two high-side power MOSFETs and two low-side drivers
for the external N-channel MOSFETs. The two pulse-width mod-
ulation (PWM) channels can be configured to deliver dual 3 A
outputs or a parallel-to-single 6 A output. The regulator operates
from input voltages of 4.5 V to 20 V, and the output voltage can
be as low as 0.6 V.
The switching frequency can be programmed between 250 kHz
and 1.2 MHz, or synchronized to an external clock to minimize
interference in multirail applications. The dual PWM channels
run 180° out of phase, thereby reducing input current ripple as
well as reducing the size of the input capacitor.
The bidirectional synchronization pin can be programmed at
a 60°, 90°, or 120° phase shift, providing the possibility for a
stackable multiphase power solution.
The ADP2323 can be set to operate in pulse-frequency modulation
(PFM) mode at a light load for higher efficiency or in forced
PWM for noise sensitive applications. External compensation
and soft start provide design flexibility. Independent enable
TYPICAL APPLICATION CIRCUIT
RTOP1
RBOT1
CC1
RC1 CSS1
VIN
CIN1
CINT
CDRV
ROSC
INTVCC
MODE
SCFG
TRK2
TRK1
VDRV
GND
PGOOD2
PGOOD1
SYNC
RT
ADP2323
SW1
CBST1
L1
M1
DL1
PGND
DL2
M2
SW2
L2
CBST2
RBOT2
RTOP2
RC2
CC2
CSS2
CIN2
VIN
VOUT1
COUT1
COUT2
VOUT2
Figure 1.
inputs and power good outputs provide reliable power sequencing.
To enhance system reliability, the device also includes undervoltage
lockout (UVLO), overvoltage protection (OVP), overcurrent pro-
tection (OCP), and thermal shutdown (TSD).
The ADP2323 operates over the −40°C to +125°C junction
temperature range and is available in a 32-lead LFCSP_WQ
package.
100
95
90
85
80
75
70
65
60 VOUT = 5V
VOUT = 3.3V
55
50
0
0.5 1.0 1.5 2.0 2.5 3.0
OUTPUT CURRENT (A)
Figure 2. Efficiency vs. Output Current at VIN = 12 V, fSW = 600 kHz
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2011–2012 Analog Devices, Inc. All rights reserved.
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ADP2323 Datasheet, Funktion
ADP2323
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
PVIN1, PVIN2, EN1, EN2
SW1, SW2
BST1, BST2
FB1, FB2, SS1, SS2,COMP1, COMP2,
PGOOD1, PGOOD2, TRK1, TRK2, SCFG,
SYNC, RT, MODE
INTVCC, VDRV, DL1, DL2
PGND to GND
Temperature Range
Operating (Junction)
Storage
Soldering Conditions
Rating
−0.3 V to +22 V
−1 V to +22 V
VSW + 6 V
−0.3 V to +6 V
−0.3 V to +6 V
−0.3 V to +0.3 V
−40°C to +125°C
−65°C to +150°C
JEDEC J-STD-020
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Data Sheet
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Boundary Condition
θJA is measured using natural convection on a JEDEC 4-layer
board, and the exposed pad is soldered to the printed circuit
board (PCB) with thermal vias.
Table 3. Thermal Resistance
Package Type
32-Lead LFCSP_WQ
θJA
32.7
Unit
°C/W
ESD CAUTION
Rev. A | Page 6 of 32
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ADP2323 pdf, datenblatt
ADP2323
5.8
5.6
5.4
5.2
5.0
4.8
4.6
4.4
4.2
4.0
–40 –20 0 20 40 60 80 100 120
TEMPERATURE (°C)
Figure 23. Current-Limit Threshold vs. Temperature, RILIM = Floating
2.0
1.8
1.6
1.4
1.2
1.0
0.8
–40 –20 0 20 40 60 80 100 120
TEMPERATURE (°C)
Figure 24. Current-Limit Threshold vs. Temperature, RILIM = 15 kΩ
VOUT (AC)
1
IL
4
2
SW
CH1 10.0mV BW CH2 10.0V M2.00µs A CH2 9.40V
CH4 500mA Ω T 50.20%
Figure 25. Discontinuous Conduction Mode (DCM)
Data Sheet
3.2
3.1
3.0
2.9
2.8
2.7
2.6
2.5
–40 –20 0 20 40 60 80 100 120
TEMPERATURE (°C)
Figure 26. Current-Limit Threshold vs. Temperature, RILIM = 47 kΩ
VOUT (AC)
1
IL
4
2
SW
CH1 10.0mV BW CH2 10.0V
M2.00µs A CH2 5.80V
CH4 2.00A Ω T 50.00%
Figure 27. Continuous Conduction Mode (CCM)
1
VOUT (AC)
IL
4
SW
2
CH1 100mV
BW CH2 10.0V M400µs A CH1
CH4 1.00A Ω T 60.40%
Figure 28. Power Saving Mode
–12.0mV
Rev. A | Page 12 of 32
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