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PDF ADP7182 Data sheet ( Hoja de datos )
| Número de pieza | ADP7182 | |
| Descripción | Linear Regulator | |
| Fabricantes | Analog Devices | |
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Data Sheet
–28 V, −200 mA, Low Noise, Linear
Regulator
ADP7182
FEATURES
Low noise: 18 µV rms
Power supply rejection ratio (PSRR): 66 dB at 10 kHz at VOUT = −3 V
Positive or negative enable logic
Stable with small 2.2 µF ceramic output capacitor
Input voltage range: −2.7 V to −28 V
Maximum output current: −200 mA
Low dropout voltage: −185 mV at −200 mA load
Initial accuracy: ±1%
Accuracy over line, load, and temperature
+2% maximum/−3% minimum
Low quiescent current, IGND = −650 µA with −200 mA load
Low shutdown current: −2 µA
Adjustable output from −1.22 V to −VIN + VDO
Current-limit and thermal overload protection
8-lead LFCSP and 5-lead TSOT
APPLICATIONS
Regulation to noise sensitive applications
Analog-to-digital converter (ADC) and digital-to-analog
converter (DAC) circuits, precision amplifiers
Communications and infrastructure
Medical and healthcare
Industrial and instrumentation
TYPICAL APPLICATION CIRCUITS
CIN
2.2µF
COUT
2.2µF
GND
VIN = –8V
VIN VOUT
VOUT = –5V
ON
2V
ADP7182
OFF
0V
EN
NC
–2V
ON
Figure 1. ADP7182 with Fixed Output Voltage, VOUT = −5 V
CIN
2.2µF
COUT
2.2µF
13kΩ
VIN = –8V
GND
VIN VOUT
40.2kΩ
VOUT = –5V
ON
2V
ADP7182
OFF
0V
EN ADJ
–2V
ON
Figure 2. ADP7182 with Adjustable Output Voltage, VOUT = −5 V
GENERAL DESCRIPTION
The ADP7182 is a CMOS, low dropout (LDO) linear regulator
that operates from −2.7 V to −28 V and provides up to −200 mA
of output current. This high input voltage LDO is ideal for
regulation of high performance analog and mixed signal circuits
operating from −27 V down to −1.22 V rails. Using an advanced
proprietary architecture, it provides high power supply rejection
and low noise, and achieves excellent line and load transient
response with a small 2.2 µF ceramic output capacitor.
The ADP7182 is available in a fixed output voltage and an
adjustable version that allows the output voltage to range from
−1.22 V to −VIN + VDO via an external feedback divider.
The ADP7182 regulator output noise is 18 µV rms independent
of the output voltage. The enable logic is capable of interfacing
with positive or negative logic levels for maximum flexibility.
The ADP7182 is available in an 8-lead LFCSP package for a
small, low profile footprint. The 5-lead TSOT package is
scheduled for release by the end of 2013.
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
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1 page  
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
VIN to GND
VOUT to GND
EN to GND
EN to VIN
ADJ to GND
Storage Temperature Range
Operating Junction Temperature Range
Operating Ambient Temperature Range
Soldering Conditions
Rating
+0.3 V to −30 V
0.3 V to VIN
5 V to VIN
+30 V to −0.3 V
+0.3 V to VOUT
−65°C to +150°C
−40°C to +125°C
−40°C to +85°C
JEDEC J-STD-020
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL DATA
Absolute maximum ratings apply individually only, not in
combination. The ADP7182 can be damaged when the junction
temperature limits are exceeded. Monitoring ambient temperature
does not guarantee that junction temperature (TJ) is within the
specified temperature limits. In applications with high power
dissipation and poor thermal resistance, the maximum ambient
temperature may have to be derated.
In applications with moderate power dissipation and low printed
circuit board (PCB) thermal resistance, the maximum ambient
temperature can exceed the maximum limit as long as the junction
temperature is within specification limits. The TJ of the device is
dependent on the ambient temperature (TA), the power dissipation
of the device (PD), and the junction-to-ambient thermal resistance
of the package (θJA).
Maximum TJ is calculated from the TA and PD using the formula
TJ = TA + (PD × θJA)
Junction-to-ambient thermal resistance (θJA) of the package is
based on modeling and calculation using a 4-layer board. The
junction-to-ambient thermal resistance is highly dependent
on the application and board layout. In applications where high
maximum power dissipation exists, close attention to thermal
ADP7182
board design is required. The value of θJA may vary, depending
on PCB material, layout, and environmental conditions. The
specified values of θJA are based on a 4-layer, 4 in. × 3 in. circuit
board. See JESD51-7 and JESD51-9 for detailed information on the
board construction. For additional information, see the AN-617
Application Note , MicroCSP™ Wafer Level Chip Scale Package.
ΨJB is the junction-to-board thermal characterization parameter
with units of °C/W. ΨJB of the package is based on modeling and
calculation using a 4-layer board. The JESD51-12, Guidelines for
Reporting and Using Electronic Package Thermal Information,
states that thermal characterization parameters are not the same
as thermal resistances. ΨJB measures the component power
flowing through multiple thermal paths rather than a single
path as in thermal resistance, θJB. Therefore, ΨJB thermal paths
include convection from the top of the package as well as
radiation from the package, factors that make ΨJB more useful
in real-world applications. Maximum junction temperature is
calculated from the board temperature (TB) and power dissipation
using the formula
TJ = TB + (PD × ΨJB)
See JESD51-8 and JESD51-12 for more detailed information
about ΨJB.
THERMAL RESISTANCE
θJA, θJC, and ΨJB are specified for the worst-case conditions, that is, a
device soldered in a circuit board for surface-mount packages.
Table 4. Thermal Resistance
Package Type
θJA θJC
8-Lead LFCSP
50.2 31.7
5-Lead TSOT
170 Not applicable
ΨJB Unit
18.2 °C/W
43 °C/W
ESD CAUTION
Rev. A | Page 5 of 28
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Data Sheet
0
–200
–400
–600
–800
–1000
–1200
–1400
–1600
–5.4
ILOAD = –5mA
ILOAD = –10mA
ILOAD = –25mA
ILOAD = –50mA
ILOAD = –100mA
ILOAD = –200mA
–5.2
–5.0
–4.8
VIN (V)
Figure 25. Ground Current vs. Input Voltage (VIN) in Dropout, VOUT = −5 V
–1.770
–1.775
–1.780
–1.785
ILOAD = –100µA
ILOAD = –1mA
ILOAD = –10mA
ILOAD = –50mA
ILOAD = –100mA
ILOAD = –200mA
–1.790
–1.795
–1.800
–1.805
–1.810
–40 –5 25 85 125
JUNCTION TEMPERATURE (°C)
Figure 26. Output Voltage (VOUT) vs. Junction Temperature (TJ), VOUT = −1.8 V
–1.790
–1.795
–1.800
–1.805
–1.810
–200
–150
–100
–50
0
ILOAD (mA)
Figure 27. Output Voltage (VOUT) vs. Load Current (ILOAD), VOUT = −1.8 V
ADP7182
–1.780
–1.785
–1.790
–1.795
–1.800
–1.805
–1.810
–30
ILOAD = –100µA
ILOAD = –1mA
ILOAD = –10mA
–25 –20
ILOAD = –50mA
ILOAD = –100mA
ILOAD = –200mA
–15 –10
–5
0
VIN (V)
Figure 28. Output Voltage (VOUT) vs. Input Voltage (VIN), VOUT = −1.8 V
0
–100
–200
–300
–400
–500
–600
ILOAD = –100µA
ILOAD = –1mA
ILOAD = –10mA
ILOAD = –50mA
ILOAD = –100mA
ILOAD = –200mA
–700
–40 –5 25 85 125
JUNCTION TEMPERATURE (°C)
Figure 29. Ground Current vs. Junction Temperature (TJ), VOUT = −1.8 V
0
–100
–200
–300
–400
–500
–600
–700
–200
–150
–100
–50
0
ILOAD (mA)
Figure 30. Ground Current vs. Load Current (ILOAD), VOUT = −1.8 V
Rev. A | Page 11 of 28
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