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PDF ADF4351 Data sheet ( Hoja de datos )
| Número de pieza | ADF4351 | |
| Descripción | Wideband Synthesizer | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Data Sheet
Wideband Synthesizer
with Integrated VCO
ADF4351
FEATURES
GENERAL DESCRIPTION
Output frequency range: 35 MHz to 4400 MHz
Fractional-N synthesizer and integer-N synthesizer
Low phase noise VCO
Programmable divide-by-1/-2/-4/-8/-16/-32/-64 output
Typical jitter: 0.3 ps rms
Typical EVM at 2.1 GHz: 0.4%
Power supply: 3.0 V to 3.6 V
Logic compatibility: 1.8 V
Programmable dual-modulus prescaler of 4/5 or 8/9
Programmable output power level
RF output mute function
3-wire serial interface
Analog and digital lock detect
Switched bandwidth fast lock mode
Cycle slip reduction
The ADF4351 allows implementation of fractional-N or integer-N
phase-locked loop (PLL) frequency synthesizers when used with
an external loop filter and external reference frequency.
The ADF4351 has an integrated voltage controlled oscillator (VCO)
with a fundamental output frequency ranging from 2200 MHz to
4400 MHz. In addition, divide-by-1/-2/-4/-8/-16/-32/-64 circuits
allow the user to generate RF output frequencies as low as 35 MHz.
For applications that require isolation, the RF output stage can be
muted. The mute function is both pin- and software-controllable.
An auxiliary RF output is also available, which can be powered
down when not in use.
Control of all on-chip registers is through a simple 3-wire interface.
The device operates with a power supply ranging from 3.0 V to
3.6 V and can be powered down when not in use.
APPLICATIONS
Wireless infrastructure (W-CDMA, TD-SCDMA, WiMAX,
GSM, PCS, DCS, DECT)
Test equipment
Wireless LANs, CATV equipment
Clock generation
SDVDD
FUNCTIONAL BLOCK DIAGRAM
AVDD
DVDD
VP RSET VVCO
REFIN
CLK
DATA
LE
×2
DOUBLER
10-BIT R
COUNTER
÷2
DIVIDER
DATA REGISTER
FUNCTION
LATCH
INTEGER FRACTION MODULUS
VALUE
VALUE
VALUE
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
N COUNTER
LOCK
DETECT
MULTIPLEXER
CHARGE
PUMP
PHASE
COMPARATOR
VCO
CORE
FAST LOCK
SWITCH
÷1/2/4/8/16/
32/64
OUTPUT
STAGE
OUTPUT
STAGE
MUXOUT
SW
LD
CPOUT
VTUNE
VREF
VCOM
TEMP
RFOUTA+
RFOUTA–
PDBRF
RFOUTB+
RFOUTB–
MULTIPLEXER
ADF4351
CE AGND
DGND
CPGND
Figure 1.
SDGND AGNDVCO
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2012 Analog Devices, Inc. All rights reserved.
Free Datasheet http://www.Datasheet4U.com
1 page  
Data Sheet
ADF4351
TIMING CHARACTERISTICS
AVDD = DVDD = VVCO = SDVDD = VP = 3.3 V ± 10%; AGND = DGND = 0 V; 1.8 V and 3 V logic levels used; TA = TMIN to TMAX, unless
otherwise noted.
Table 2.
Parameter
t1
t2
t3
t4
t5
t6
t7
Limit
20
10
10
25
25
10
20
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Description
LE setup time
DATA to CLK setup time
DATA to CLK hold time
CLK high duration
CLK low duration
CLK to LE setup time
LE pulse width
Timing Diagram
CLK
t4 t5
DATA
DB31 (MSB)
t2 t3
DB30
DB2
(CONTROL BIT C3)
DB1
(CONTROL BIT C2)
LE
t1
LE
Figure 2. Timing Diagram
DB0 (LSB)
(CONTROL BIT C1)
t7
t6
Rev. 0 | Page 5 of 28
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5 Page 
Data Sheet
ADF4351
CIRCUIT DESCRIPTION
REFERENCE INPUT SECTION
The reference input stage is shown in Figure 16. The SW1 and
SW2 switches are normally closed. The SW3 switch is normally
open. When power-down is initiated, SW3 is closed, and SW1
and SW2 are opened. In this way, no loading of the REFIN pin
occurs during power-down.
POWER-DOWN
CONTROL
NC 100kΩ
REFIN NC
SW2
SW1
SW3
NO
TO R COUNTER
BUFFER
Figure 16. Reference Input Stage
RF N DIVIDER
The RF N divider allows a division ratio in the PLL feedback
path. The division ratio is determined by the INT, FRAC, and
MOD values, which build up this divider (see Figure 17).
FROM
VCO OUTPUT/
OUTPUT DIVIDERS
RF N DIVIDER
N COUNTER
N = INT + FRAC/MOD
TO PFD
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
INT
VALUE
FRAC
VALUE
MOD
VALUE
The PFD frequency (fPFD) equation is
fPFD = REFIN × [(1 + D)/(R × (1 + T))]
(2)
where:
REFIN is the reference input frequency.
D is the REFIN doubler bit (0 or 1).
R is the preset divide ratio of the binary 10-bit programmable
reference counter (1 to 1023).
T is the REFIN divide-by-2 bit (0 or 1).
Integer-N Mode
If FRAC = 0 and the DB8 (LDF) bit in Register 2 is set to 1, the
synthesizer operates in integer-N mode. The DB8 bit in Register 2
should be set to 1 for integer-N digital lock detect.
R Counter
The 10-bit R counter allows the input reference frequency
(REFIN) to be divided down to produce the reference clock
to the PFD. Division ratios from 1 to 1023 are allowed.
PHASE FREQUENCY DETECTOR (PFD) AND
CHARGE PUMP
The phase frequency detector (PFD) takes inputs from the
R counter and N counter and produces an output proportional
to the phase and frequency difference between them. Figure 18
is a simplified schematic of the phase frequency detector.
HIGH
UP
D1 Q1
U1
+IN CLR1
Figure 17. RF N Divider
INT, FRAC, MOD, and R Counter Relationship
The INT, FRAC, and MOD values, in conjunction with the
R counter, make it possible to generate output frequencies that
are spaced by fractions of the PFD frequency. For more informa-
tion, see the RF Synthesizer—A Worked Example section.
The RF VCO frequency (RFOUT) equation is
RFOUT = fPFD × (INT + (FRAC/MOD))
(1)
where:
RFOUT is the output frequency of the voltage controlled oscillator
(VCO).
INT is the preset divide ratio of the binary 16-bit counter (23 to
65,535 for the 4/5 prescaler; 75 to 65,535 for the 8/9 prescaler).
FRAC is the numerator of the fractional division (0 to MOD − 1).
MOD is the preset fractional modulus (2 to 4095).
DELAY U3
CHARGE
PUMP
CPOUT
HIGH
CLR2 DOWN
D2 Q2
U2
–IN
Figure 18. PFD Simplified Schematic
The PFD includes a programmable delay element that sets the
width of the antibacklash pulse (ABP). This pulse ensures that
there is no dead zone in the PFD transfer function. Bit DB22 in
Register 3 (R3) is used to set the ABP as follows:
• When Bit DB22 is set to 0, the ABP width is programmed to
6 ns, the recommended value for fractional-N applications.
• When Bit DB22 is set to 1, the ABP width is programmed to
3 ns, the recommended value for integer-N applications.
For integer-N applications, the in-band phase noise is improved
by enabling the shorter pulse width. The PFD frequency can
operate up to 90 MHz in this mode. To operate with PFD
frequencies higher than 45 MHz, VCO band select must be dis-
abled by setting the phase adjust bit (DB28) to 1 in Register 1.
Rev. 0 | Page 11 of 28
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| PDF Descargar | [ Datasheet ADF4351.PDF ] | |
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