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PDF PE12316 Data sheet ( Hoja de datos )
| Número de pieza | PE12316 | |
| Descripción | Triple Incremental Encoder | |
| Fabricantes | Adronic Components | |
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February 6, 2003 Preliminary (Version 1.1)
Features:
• Functional and pincompatible with TI
CF32006 / THCT12316
• Three independent channels in one device
• Each channel compatible with PE12016
• Available as IP-Core or within PLCC68
Package
• Interfaces three mechanisms / axes to data
bus
• Pulse width measurement
• Frequency measurement
PE12316
Triple
Incremental Encoder
• Cascadable 16-bit counters
• TTL compatible
• 5V and 3.3V Operation
• 8 Bit parallel tristatable Bus
• Simple read & write procedure
• High speed 20 MHz clock operation
• Direction discriminators identify &
measure forward/backward rotation
• separate zero pulse input
New Feature:
• Each channel extendable to 24 Bit
A1
A2
CS
GND
D0
D1
VCC
D2
D3
GND
D4
D5
VCC
D6
D7
GND
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
PE12316
PLCC68
60 KLI-KLO3
59 CARRY1
58 BORROW1
57 CARRY2
56 BORROW2
55 CARRY3
54 BORROW3
53 GND
52 VCC
51 DOWN3
50 UP3
49 DOWN2
48 UP2
47 DOWN1
46 UP1
45 Ua23
44 Ua13
Figure 1 Pinout
NC Pins should be left open
and not connected to the
PCB. They are reserved for
future upgrades.
Description:
The PE12316 TRIPLE INCREMENTAL ENCODER INTERFACE consists of three channels each,
which can independently determine the direction of displacement of a mechanical or axis based device
on two input signals from transducers in quadrature. Alternatively, each channel can measure a pulse
width using a known clock rate, or a frequency, by counting input pulses over a known time interval. It
includes three 16/24-bit counters which may also be used separately. The PE12316 may be cascaded
between channels on one device or between devices to provide accuracy greater than 16/24-bits, and
is designed for use in many microprocessor-based systems.
February 6, 2003 (Preliminary Version 1.1)
Page 1/29
PE12316
Free Datasheet http://www.Datasheet4U.com
1 page  
February 6, 2003 Preliminary (Version 1.1)
PE12316
Triple
Incremental Encoder
Operation:
The eight modes of operation of the PE12316
are summarized in Table 1.
The modes of the three channels can be
selected independently.
Mode
0
M2n M1n M0n
Mode Description
COUNTER
0 0 0 16-bit up/down counter (inhibits direction discriminator)
DIRECTION DISCRIMINATOR
1 0 0 1 Single count pulse synchronous with Ua1n rising in forward
direction and Ua1n falling in backward direction.
2 0 1 0 Single count pulse synchronous with Ua2n rising in forward
direction and Ua2n falling in backward direction.
3 0 1 1 Double count pulse synchronous with Ua1n rising and falling.
4 1 0 0 Double count pulse synchronous with Ua2n rising and falling.
5 1 0 1 Quadruple count pulse synchronous with all edges.
PULSE WIDTH MEASUREMENT
6 1 1 0 Ua1n is the gate signal
Ua2n is high for up counting and low for down counting.
Count is synchronous with rising clock.
FREQUENCY MEASUREMENT
7 1 1 1 Ua1n is frequency signal to be measured
Ua2n is the gate signal of known time interval.
Count is synchronous with rising edge of Ua1n.
Table 1 Mode Description
February 6, 2003 (Preliminary Version 1.1)
Page 5/29
PE12316
Free Datasheet http://www.Datasheet4U.com
5 Page 
February 6, 2003 Preliminary (Version 1.1)
PE12316
Triple
Incremental Encoder
Reset Operation:
A total reset is initiated by pulling the /RESET
pin low. This will clear the counters to zero,
reset the D flip-flops at the inputs of the
quadrature signals (Ua1n and Ua2n), clear the
latches that inhibit the load register pulse, and
load zero into the output register.
To avoid a spurious count error (+/- 1) after a
reset, the Ua1n and Ua2n inputs should be held
to the values indicated in
Table 4 during and just after the reset pulse.
MODE
0
1-5
6-7
Ua1n
X
H
L
Ua2n
X
H
L
Table 4 Mode Selection
Cascading Devices
The /KLI-KLOn pins of all cascaded PE12316’s
should be tied together, so that all of the devices
load their output registers at the same time.
When the ‘Master’ generates a pulse for the
other PE12316s, /KLI-KLOn on the ‘Master’
works as an output, and /KLI-KLOn on the
‘Slaves’ work as inputs. The /CARRY output of
one device should be tied to the /UP input of the
next device in the cascade. Similarly, /BORROW
should be connected to /DOWN. For details see
Figure 14.
Write Operation
A number may be preloaded into the counter by
pulling /CS and /WE low while using /A0 and /A3
to direct the value on the data bus to the
selected byte of the counter and /A1 & /A2 to
select the required
channel. This will cause /READY to go low on the
next falling clock edge, and remain low until /CS
and /WE go high. See Figure 12.
Read Operation
When in Modes 0 to 5 the contents of the
counter can be read at any time by pulling /CS
and /RD low. The channel is selected by using
/A1 & /A2. Within this channel the most
significant byte may be selected by setting /A3 to
low, and the least significant byte may be read
by setting /A0 and /A3 high. This will cause a
load output register pulse to be generated and
/KLI-KLOn will go low during the next low clock
pulse. /READY will also go low as the clock goes
low, and will stay low until /CS and/or /RD go
high.
The load output register pulse stores the current
value of the counter in a 16-bit latch register and
/A0 /A3 direct the selected byte through a
multiplexer to the outputs : /CS and /RD also
enable the 3-stat outputs – see Figure 11. The
output register will be loaded immediately if /KLI-
KLOn is pulled low externally, this signal normally
comes from a cascaded device.
For Modes 6 & 7 see the earlier description.
February 6, 2003 (Preliminary Version 1.1)
Page 11/29
PE12316
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