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PDF AX88180 Data sheet ( Hoja de datos )
| Número de pieza | AX88180 | |
| Descripción | High-Performance Non-PCI 32-bit 10/100/1000M Gigabit Ethernet Controller | |
| Fabricantes | ASIX | |
| Logotipo |  |
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AX88180
High-Performance Non-PCI
32-bit 10/100/1000M Gigabit Ethernet Controller
Document No: AX88180/V1.4
Features
● High-performance non-PCI local bus
Support 10/100/1000Mbps data rate with RGMII
16/32-bit SRAM-like host interface
or MII in 10/100Mbps data rate.
Support big/little endian data bus type
Support back-pressure flow control for half-duplex
Large embedded SRAM for packet buffers
operation
32K bytes for receive buffer
Support packet length set by software
8K bytes for transmit buffer
Support max 4K bytes JUMBO packet
Support IP/TCP/UDP checksum offloads
● Support Wake-on-LAN function by following events
Support interrupt with high or low active trigger
Detection of network link-up state
mode
Receipt of a Magic Packet
● Highly-integrated Gigabit Ethernet controller
● Support Magic Packet detection for remote wake-up
Compatible with IEEE802.3, 802.3u, and 802.3ab after power–on reset
standards
● Support EEPROM interface
Support 10/100/1000Mbps data rate
● Support PCMCIA in 16-bit mode
Support full duplex operation with 1000Mbps data ● Support synchronous or asynchronous mode to host
rate MCU
Support full and half duplex operations with ● Integrated voltage regulator from 3.3V to 2.5V
10/100Mbps date rate
● 2.5V for core and 3.3V I/O with 5V tolerance
Support 10/100/1000Mbps N-way Auto-negotiation ● 128-pin LQFP with CMOS process, RoHS package
operation
● US patent approved (NO 6799231)
Support IEEE 802.3x flow control for full-duplex
operation
Product Description
The AX88180 is a high-performance and cost-effective non-PCI Gigabit Ethernet controller for various embedded
systems including consumer electronics and home network markets that require a higher bandwidth of network
connectivity. The AX88180 supports 16/32-bit SRAM-like host interface and Gigabit Ethernet MAC, which is
IEEE802.3 10Base-T, IEEE802.3u 100Base-T, and IEEE802.3ab 1000Base-T compatible. The AX88180 supports
full-duplex or half-duplex operation at 10/100/1000Mbps speed with auto-negotiation or manual setting. The AX88180
integrates large embedded SRAM for packet buffers to accommodate high bandwidth applications and supports
IP/TCP/UDP checksum to offload processing loading from microprocessor/microcontroller in an embedded system
System Block Diagram
Always contact ASIX for possible updates before starting a design.
This data sheet contains new products information. ASIX ELECTRONICS reserves the rights to modify product
specification without notice. No liability is assumed as a result of the use of this product. No rights under any patent
accompany the sale of the product.
ASIX ELECTRONICS CORPORATION
4F, NO.8, Hsin Ann Rd., Hsinchu Science Park, Hsinchu, Taiwan, R.O.C.
TEL: 886-3-579-9500
FAX: 886-3-579-9558
Released Date: 5/18/2007
http://www.asix.com.tw
Free Datasheet http://www.Datasheet4U.com
1 page  
AX88180
Revision History .....................................................................................................................................................................46
List of Figures
Figure 1 : AX88180 block diagram ...................................................................................................................................... 6
Figure 2 : AX88180 pin connection diagram........................................................................................................................ 7
Figure 3: 32-bit mode address mapping................................................................................................................................ 12
Figure 4: data swap block ..................................................................................................................................................... 13
Figure 5: 16-bit mode memory mapping .............................................................................................................................. 14
List of Tables
Table 1 : RGMII/MII Interface signals group ...........................................................................................................................8
Table 2 : Host Interface signals group ......................................................................................................................................9
Table 3 : EEPROM Interface signals group............................................................................................................................10
Table 4 : Regulator signals group ...........................................................................................................................................10
Table 5 : Miscellaneous signals group ....................................................................................................................................11
Table 6 : Power/Ground pins group ........................................................................................................................................11
Table 7: MAC Register Mapping............................................................................................................................................15
5 ASIX ELECTRONICS CORPORATION
Free Datasheet http://www.Datasheet4U.com
5 Page 
AX88180
2.6 Miscellaneous
Pin Name
Table 5 : Miscellaneous signals group
Type Pin No. Pin Description
GPIO0
GPIO1
TEST0
IO3,
12mA,
PD
IO3,
12mA,
PD
I3, PD
55
54
52
General Purpose pin. In reset stage this pin defines chip operates in 16 or 32-bit mode.
Pull-down is for 32-bit mode and pull-up (by 4.7K) is for 16-bit mode. If this pin is
floating, it will be as default for 32-bit mode.
General Purpose pin. In reset stage this pin defines chip operates in little-endian or
big-endian mode. Pull-down is little-endian mode and pull-up is big-endian mode. If
this pin is floating, it will as default for little-endian mode.
Connect to ground for normal operation.
TEST1
I3, PD 53
Connect to ground for normal operation.
TEST2
I25 83
Connect to ground for normal operation.
TEST3
I25 84
Connect to ground for normal operation.
TEST4
I25 88
Pull-down for normal operation
TEST5
I25 90
Connect to ground for normal operation.
TEST6
I25 97
Pull-up (with 4.7K) for normal operation
NC O 91,93,94 No connection
2.7 Power/ground pin
Table 6 : Power/Ground pins group
Pin Name
VCC33
VCC25
GND
Type
VCC3
VCC2
GND
Pin No.
1,13,40, 105, 119
4,20,27,35,57,60,64,72,78,81,85,89,96,98,100,107,
117,123
8,56,73,82,86,87,92,95,99,101,106
Pin Description
3.3V power pins
2.5V power pins
Ground pins
11 ASIX ELECTRONICS CORPORATION
Free Datasheet http://www.Datasheet4U.com
11 Page | ||
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