PDF AD9656 Data sheet ( Hoja de datos )

Número de pieza	AD9656
Descripción	1.8 V Analog-to-Digital Converter
Fabricantes	Analog Devices
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Data Sheet Quad, 16-Bit, 125 MSPS, JESD204B 1.8 V Analog-to-Digital Converter AD9656 FEATURES SNR = 79.9 dBFS at 16 MHz (VREF = 1.4 V) SNR = 78.1 dBFS at 64 MHz (VREF = 1.4 V) SFDR = 86 dBc to Nyquist (VREF = 1.4 V) JESD204B Subclass 1 coded serial digital outputs Flexible analog input range: 2.0 V p-p to 2.8 V p-p 1.8 V supply operation Low power: 197 mW per channel at 125 MSPS (two lanes) DNL = ±0.6 LSB (VREF = 1.4 V) INL = ±4.5 LSB (VREF = 1.4 V) 650 MHz analog input bandwidth, full power Serial port control Full chip and individual channel power-down modes Built-in and custom digital test pattern generation Multichip sync and clock divider Standby mode APPLICATIONS Medical imaging High speed imaging Quadrature radio receivers Diversity radio receivers Portable test equipment GENERAL DESCRIPTION The AD9656 is a quad, 16-bit, 125 MSPS analog-to-digital converter (ADC) with an on-chip sample-and-hold circuit designed for low cost, low power, small size, and ease of use. The device operates at a conversion rate of up to 125 MSPS and is optimized for outstanding dynamic performance and low power in applications where a small package size is critical. The ADC requires a single 1.8 V power supply and LVPECL-/ CMOS-/LVDS-compatible sample rate clock for full performance operation. No external reference or driver components are required for many applications. Individual channel power-down is supported and typically consumes less than 14 mW when all channels are disabled. The ADC contains several features designed to maximize flexibility and minimize system cost, such as a programmable output clock, data alignment, and digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI). FUNCTIONAL BLOCK DIAGRAM AVDD PDWN DVDD DRVDD VINA+ VINA– VINB+ VINB– RBIAS VREF SENSE AGND VINC+ VINC– VIND+ VIND– 16 PIPELINE ADC 16 PIPELINE ADC JESD204B INTERFACE REF SELECT 1V TO 1.4V HIGH SPEED SERIALIZERS 16 PIPELINE ADC 16 PIPELINE ADC CONTROL REGISTERS CML TX OUTPUTS VCM SERIAL PORT INTERFACE CLOCK MANAGEMENT AD9656 SERDOUT0+ SERDOUT0– SERDOUT1+ SERDOUT1– SERDOUT2+ SERDOUT2– SERDOUT3+ SERDOUT3– DSYNC+ DSYNC– Figure 1. The AD9656 is available in an RoHS-compliant, nonmagnetic, 56-lead LFCSP. It is specified over the −40°C to +85°C industrial temperature range. This product is protected by a U.S. patent. PRODUCT HIGHLIGHTS 1. It has a small footprint. Four ADCs are contained in a small, 8 mm × 8 mm package. 2. An on-chip phase-locked loop (PLL) allows users to provide a single ADC sampling clock; the PLL multiplies the ADC sampling clock to produce the corresponding JESD204B data rate clock. 3. The configurable JESD204B output block supports up to 6.4 Gbps per lane. 4. JESD204B output block supports one, two, and four lane configurations. 5. Low power of 198 mW per channel at 125 MSPS, two lanes. 6. The SPI control offers a wide range of flexible features to meet specific system requirements. Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com Free Datasheet http://www.Datasheet4U.com 1 page Data Sheet AD9656 AC SPECIFICATIONS, VREF = 1.4 V AVDD = 1.8 V, DRVDD = 1.8 V, 2.8 V p-p full-scale differential input, 1.4 V reference, AIN = −1.0 dBFS, unless otherwise noted. Table 3. Parameter1 SIGNAL-TO-NOISE RATIO (SNR) fIN = 9.7 MHz fIN = 16 MHz fIN = 64 MHz fIN = 128 MHz fIN = 201 MHz fIN = 301 MHz SIGNAL-TO-NOISE-AND-DISTORTION (SINAD) RATIO fIN = 9.7 MHz fIN = 16 MHz fIN = 64 MHz fIN = 128 MHz fIN = 201 MHz fIN = 301 MHz EFFECTIVE NUMBER OF BITS (ENOB) fIN = 9.7 MHz fIN = 16 MHz fIN = 64 MHz fIN = 128 MHz fIN = 201 MHz fIN = 301 MHz SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 9.7 MHz fIN = 16 MHz fIN = 64 MHz fIN = 128 MHz fIN = 201 MHz fIN = 301 MHz WORST HARMONIC (SECOND OR THIRD) fIN = 9.7 MHz fIN = 16 MHz fIN = 64 MHz fIN = 128 MHz fIN = 201 MHz fIN = 301 MHz WORST OTHER HARMONIC (EXCLUDING SECOND OR THIRD) fIN = 9.7 MHz fIN = 16 MHz fIN = 64 MHz fIN = 128 MHz fIN = 201 MHz fIN = 301 MHz TWO-TONE INTERMODULATION DISTORTION (IMD)—INPUT AMPLITUDE = −7.0 dBFS fIN1 = 70.5 MHz, fIN2 = 72.5 MHz Temperature Min Typ Max 25°C 80.1 25°C 79.9 25°C 75.7 78.1 25°C 75 25°C 72.7 25°C 69.7 25°C 79.6 25°C 78.4 25°C 74.8 77.3 25°C 74.4 25°C 71 25°C 68.6 25°C 12.9 25°C 12.7 25°C 12.1 12.5 25°C 12.1 25°C 11.5 25°C 11.1 25°C 89 25°C 87 25°C 78 86 25°C 84 25°C 76 25°C 75 25°C −89 25°C −87 25°C −86 −78 25°C −84 25°C −76 25°C −75 25°C −96 25°C −92 25°C −90 −87 25°C −89 25°C −93 25°C −90 25°C −84 Unit dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS Bits Bits Bits Bits Bits Bits dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc Rev. 0 \| Page 5 of 44 Free Datasheet http://www.Datasheet4U.com 5 Page Data Sheet ABSOLUTE MAXIMUM RATINGS Table 8. Parameter Electrical AVDD to AGND DRVDD to AGND DVDD to DVSS SVDD to AGND Digital Outputs to AGND CLK+, CLK− to AGND VINx+, VINx− to AGND DSYSREF+, DSYSREF− to AGND DSYNC−, DSYNC+ to AGND SCLK, SDIO, CSB, PDWN to AGND SYNC to AGND RBIAS to AGND VCM, VREF, SENSE to AGND Environmental Operating Temperature Range (Ambient) Maximum Junction Temperature Lead Temperature (Soldering, 10 sec) Storage Temperature Range (Ambient) Rating −0.3 V to +2.0 V −0.3 V to +2.0 V −0.3 V to +2.0 V −0.3 V to +2.0 V −0.3 V to +2.0 V −0.3 V to +2.0 V −0.3 V to +2.0 V −0.3 V to +2.0 V −0.3 V to +2.0 V −0.3 V to +3.9 V −0.3 V to +2.0 V −0.3 V to +2.0 V −0.3 V to +2.0 V −40°C to +85°C 150°C 300°C −65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. AD9656 THERMAL RESISTANCE θJA is for a 4-layer printed circuit board (PCB) with solid ground plane (simulated). The exposed pad is soldered to the PCB ground. Table 9. Thermal Resistance Air Flow Package Velocity θJA Type (m/sec) (°C/W) 56-Lead LFCSP, 8 mm × 8 mm 0 1 2.5 22.4 19.0 17.6 θJB (°C/W)1 7.7 N/A N/A θJC Top (°C/W)1 7.42 N/A N/A θJC Bottom (°C/W)1 2.29 N/A N/A 1 N/A = not applicable. ESD CAUTION Rev. 0 \| Page 11 of 44 Free Datasheet http://www.Datasheet4U.com 11 Page

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