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ADAM22C20 Schematic ( PDF Datasheet ) - Abov

Teilenummer ADAM22C20
Beschreibung 4-BIT SINGLE CHIP MICROCOMPUTERS
Hersteller Abov
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Gesamt 30 Seiten
ADAM22C20 Datasheet, Funktion
April 30, 2008 Ver 0.0
4-BIT SINGLE CHIP MICROCOMPUTERS
ADAM22XXX
USER`S MANUAL
ADAM22C16
ADAM22P16
ADAM22C20
ADAM22P20
ADAM22C20S
ADAM22P20S
ADAM22C23
ADAM22P23
ADAM22C24
ADAM22P24






ADAM22C20 Datasheet, Funktion
ADAM22XXX
1. Overview
1.5. Pin Function
PIN
NAME
K
R0~R1
INPUT
OUTPUT
FUNCTION
Input
- 4-bit input Only Port.
- CMOS input with pull-up resistor.
- Each pin has STOP mode release function.
(It is released by “L” input at STOP mode.)
@RESET
@STOP
Input
Input
(with Pull-up) (with Pull-up)
R2~R3
-2-bit I/O Port. (Input mode is set only when
each of them output “H”)
- Each pin has STOP mode release function.
I/O - Output mode is set when each of them
Output is “L”
- When used as “output”, each pin can be set
and reset independently
Input
-
D0 ~ D3
D4 ~ D9
OSC1
Output
Input
- N-ch open drain output.
- Each pin can be set and reset independently.
Low
- Oscillator Input.
Oscillation
Low
Low or keep
status before
STOP *1
Low
OSC2
REMOUT
PGND
VDD
Output - Oscillator Output.
Output
Power
Power
- High Current Pulse Output.
-Ground pin for internal high current
N-channel transistor. (connected to GND)
- Positive power supply.
Oscillation
High
‘Hi-Z’ output ‘Hi-Z’ output
--
--
VSS
Power - Ground
--
Note:
*1. This Mask Option is not available in OTP version. In ADAM22PXX, D4~D9 output conditions
at STOP Mode is fixed to “Keep status before STOP”.
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ADAM22C20 pdf, datenblatt
ADAM22XXX
2. Architecture
2.2.2. Page address register and page buffer register :
Address one of pages #0 to #15 in the ROM by the 4-bit binary counter.
Unlike the program counter, the page address register is usually unchanged so
that the program will repeat on the same page unless a page changing command
is issued. To change the page address, take two steps such as (1) writing in the
page buffer what page to jump (execution of LPBI) and (2) execution of BR or CAL,
because instruction code is of eight bits so that page and word can not be specified
at the same time.
In case a return instruction (RTN) is executed within the subroutine that has been
called in the other page, the page address will be changed at the same time.
2.2.3. Program counter :
This 6-bit binary counter increments for each fetch to address a word in the
currently addressed page having an instruction to be next executed.
For easier programming, at turning on the power, the program counter is
reset to the zero location. The PA is also set to "0". Then the program
counter specifies the next address in random sequence.
When BR, CAL or RTN instructions are decoded, the switches on each step
are turned off not to update the address. Then, for BR or CAL, address
data are taken in from the instruction operands (a0 to a5), or for RTN, and
address is fetched from stack register No. 1.
2.2.4. Stack register :
This stack register provides three stages each for the program counter (6bits),
the page address register (4bits) and block address (1bit) so that subroutine
nesting can be made on two levels.
Page 11 of 35

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