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Teilenummer | GM8182 |
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Beschreibung | PCB LAYOUT GUIDE | |
Hersteller | Grain | |
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Gesamt 30 Seiten GM8182
PCB LAYOUT GUIDE
Application Note
Rev.: 0.1
Issue Date: November 2009
Free Datasheet http://www.0PDF.com
Free Datasheet http://www.0PDF.com
6 Page 2.1 Trace Layout and Passive Materials Selection
The GM8182 PLL1,PLL2 and PLL3 are very high speed PLL. The layout of the PLL need to take cares the
power and ground noise.
1. The PLL1 (CPU) power and ground noise don’t exceed over 100mV pk-pk.
The PLL2 (Mac, SATA) power and ground noise don’t exceed over
200mVpk-pk.
The PLL3 (Codec, Peripheral) power and ground noise don’t exceed over
200mVpk-pk.
2. The power noise of PLL1 lower bond (1.2 - 0.5 x △V) don’t under 1.08V.
The power noise of PLL2 lower bond (1.2 - 0.5 x △V) don’t under 1.08V.
The power noise of PLL3 lower bond (1.2 - 0.5 x △V) don’t under 1.08V.
3. PLL power, ground is analog signal. Don’t connect the BGA power, ground to PLL power, ground
directly.
4. The PLL power trace needs to pass through the by-pass capacitors. It’s better to use the
0.01~0.1uF capacitor and >10uF low ESR capacitor.
IP Name Release Note
www.faraday-tech.com
6
Free Datasheet http://www.0PDF.com
12 Page | ||
Seiten | Gesamt 30 Seiten | |
PDF Download | [ GM8182 Schematic.PDF ] |
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