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RDA1846 Schematic ( PDF Datasheet ) - RDA

Teilenummer RDA1846
Beschreibung Programming Guide
Hersteller RDA
Logo RDA Logo 




Gesamt 27 Seiten
RDA1846 Datasheet, Funktion
RDA1846 Programming Guide
RDA1846
The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in
part without prior written permission of RDA.
1
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RDA1846 Datasheet, Funktion
RDA1846
Figure 2. I2C Interface Read Timing Diagram
Figure 3 I2C Interface Write Combined Format
Figure 4 I2C Interface Read Combined Format
Table 2. I2C Timing Characteristics
PARAMETER
SYMBOL
SCLK Frequency
SCLK High Time
SCLK Low Time
Setup Time for START Condition
Hold Time for START Condition
Setup Time for STOP Condition
SDIO Input to SCLKSetup
SDIO Input to SCLKHold
STOP to START Time
SDIO Output Fall Time
SDIO Input, SCLK Rise/Fall Time
Input Spike Suppression
SCLK, SDIO Capacitive Loading
Digital Input Pin Capacitance
fscl
thigh
tlow
tsu:sta
thd:sta
tsu:sto
tsu:dat
thd:dat
tbuf
tf:out
tr:in / tf:in
tsp
Cb
TEST CONDITION
MIN
0
0.6
1.3
0.6
0.6
0.6
100
0
1.3
20+0.1Cb
20+0.1Cb
-
-
TYP
-
-
-
-
-
-
-
-
-
-
-
-
-
MAX
400
-
-
-
-
-
-
900
-
250
300
50
50
5
UNIT
KHz
s
s
s
s
s
ns
ns
s
ns
ns
ns
pF
pF
The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in
part without prior written permission of RDA.
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RDA1846 pdf, datenblatt
7. TX Pa_bias output voltage
RDA1846 Pa_bias pin output voltage can be controlled by 0aH [5:0].
Bit Name
Function
0aH [5:0]
pabias_voltage<5:0>
000000: 1.01V
000001:1.05V
000010:1.09V
000100: 1.18V
001000: 1.34V
010000: 1.68V
100000: 2.45V
1111111:3.13V
RDA1846
8. Subaudio
Bit
45H[2:0]
Name
c_mode<2:0>
45H[3]
ctcss_sel
45H[4] cdcss_sel
45H[7] neg_det_en
45H[11] Pos_det_en
45H[10] css_det_en
4aH[15:0] ctcss_freq<15:0>
Function
Ctcss/cdcss mode sel
x00=disable,
001=inner ctcss en,
010= inner cdcss en
101= outter ctcss en,
110=outter cdcss en
others =disable
1 = ctcss_cmp/cdcss_cmp out via gpio
0 = ctcss/cdcss sdo out vio gpio
24/23 bit cdcss code sel for both txon and rxon
1 = 24 bit code
0 = 23 bit code
If 1,cdcss inverse code will be detected at the same
time.
If 1, cdcss code will be detected.
If 1, sq detection will add ctcss/cdcss detect result,
then 1846 control 1846 voice output on or off.
Ctcss/cdcss frequency setting
Ctcss freq = ctcss_freq*2^16 khz
It must be set to 134.4Hz when use standard cdcss
mode
When use ctcss/cdcss, this register must be set both
The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in
part without prior written permission of RDA.
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