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PDF AD7992 Data sheet ( Hoja de datos )
| Número de pieza | AD7992 | |
| Descripción | 12-Bit ADC | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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2-Channel, 12-Bit ADC with I2C-Compatible
Interface in 10-Lead MSOP
AD7992
FEATURES
12-bit ADC with fast conversion time: 2 µs typ
2 single-ended analog input channels
Specified for VDD of 2.7 V to 5.5 V
Low power consumption
Fast throughput rate: up to 188 kSPS
Sequencer operation
Temperature range: −40 °C to 125 °C
Automatic cycle mode
I2C®-compatible serial interface supports standard, fast,
and high speed modes
Out-of-range indicator/alert function
Pin-selectable addressing via AS
2 versions allow 5 I2C addresses
Shutdown mode: 1 µA max
10-lead MSOP package
GENERAL DESCRIPTION
The AD7992 is a 12-bit, low power, successive approximation
ADC with an I2C-compatible interface. The part operates from
a single 2.7 V to 5.5 V power supply and features a 2 µs conver-
sion time. The part contains a 2-channel multiplexer and track-
and-hold amplifier that can handle input frequencies up to
11 MHz.
The AD7992 provides a 2-wire serial interface compatible with
I2C interfaces. The part comes in two versions, the AD7992-0
and the AD7992-1, and each version allows for at least two
different I2C addresses. The AD7992-0 supports standard and
fast I2C interface modes, and the AD7992-1 supports standard,
fast, and high speed I2C interface modes.
The AD7992 normally remains in a shutdown state while not
converting, and powers up only for conversions. The conversion
process can be controlled using the CONVST pin, by a
command mode where conversions occur across I2C write
operations, or an automatic conversion interval mode selected
through software control.
The AD7992 requires an external reference in the range of 1.2 V
to VDD. This allows the widest dynamic input range to the ADC.
On-chip limit registers can be programmed with high and low
limits for the conversion result, and an open-drain, out-of-
range indicator output (ALERT) becomes active when the
conversion result violates the programmed high or low limits.
This output can be used as an interrupt.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
VIN1
VIN2/REFIN
VDD
AS
FUNCTIONAL BLOCK DIAGRAM
GND
CONVST
AD7992
I/P
MUX
T/H
12-BIT SUCCESSIVE
APPROXIMATION
ADC
CONTROL
LOGIC
VIN2/REFIN
SOFTWARE
CONTROL
HYSTERESIS
REGISTER CH0
DATAHIGH LIMIT
REGISTER CH1
DATALOW LIMIT
REGISTER CH1
HYSTERESIS
REGISTER CH1
DATAHIGH LIMIT
REGISTER CH2
DATALOW LIMIT
REGISTER CH2
CONVERSION
RESULT
REGISTER
CONFIGURATION
REGISTER
ALERT STATUS
REGISTER
CYCLE TIMER
REGISTER
I2C INTERFACE
ALERT
SCL
SDA
GND
Figure 1.
PRODUCT HIGHLIGHTS
1. 2 µs conversion time and low power consumption.
2. I2C-compatible serial interface with pin-selectable
addresses. Two AD7992 versions allow five AD7992
devices to be connected to the same serial bus.
3. The part features automatic shutdown while not converting
to maximize power efficiency. Current consumption is
1 µA max when in shutdown mode at 3 V.
4. Reference can be driven up to the power supply.
5. Out-of-range indicator that can be software disabled or
enabled.
6. One-shot and automatic conversion rates.
7. Registers store minimum and maximum conversion
results.
Table 1. Related Products
Part Number No. of Bits
AD7998
12
AD7994
12
AD7997
10
AD7993
10
No. of Channels
8
4
8
4
Package
20-TSSOP
16-TSSOP
20-TSSOP
16-TSSOP
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2005 Analog Devices, Inc. All rights reserved.
Free Datasheet http://www.datasheetlist.com/
1 page  
AD7992
Parameter
LOGIC INPUTS (CONVST)
Input High Voltage, VINH
Input Low Voltage, VINL
Input Leakage Current, IIN
Input Capacitance, CIN3
LOGIC OUTPUTS (OPEN DRAIN)
Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output Capacitance3
Output Coding
CONVERSION RATE
Conversion Time
Throughput Rate
Mode 1 (Reading after the Conversion)
Mode 2
POWER REQUIREMENTS
VDD
IDD
Power-Down Mode, Interface Inactive
Power-Down Mode, Interface Active
Operating, Interface Inactive
Operating, Interface Active
Mode 3 (I2C Inactive, TCONVERT × 32)
POWER DISSIPATION
Fully Operational
Operating, Interface Active
Power Down, Interface Inactive
B Version Unit
2.4 V min
2.0 V min
0.8 V max
0.4 V max
±1 µA max
10 pF max
0.4 V max
0.6 V max
±1 µA max
10 pF max
Straight (Natural) Binary
2 µs typ
5 kSPS typ
21 kSPS typ
121 kSPS typ
5.5 kSPS typ
22 kSPS typ
147 kSPS typ
2.7/5.5
V min/max
1/2
0.07/0.3
0.3/0.6
0.06/0.1
0.3/0.6
0.15/0.4
0.6/1.1
0.7/1.4
0.7/1.5
µA max
mA max
mA max
mA max
mA max
mA max
mA max
mA typ
mA max
Test Conditions/Comments
VDD = 5 V
VDD = 3 V
VDD = 5 V
VDD = 3 V
VIN = 0 V or VDD
ISINK = 3 mA
ISINK = 6 mA
See the Serial Interface section
fSCL = 100 kHz
fSCL = 400 kHz
fSCL = 3.4 MHz
fSCL = 100 kHz
fSCL = 400 kHz
fSCL = 3.4 MHz , 188 kSPS typ @ 5 V
Digital inputs = 0 V or VDD
VDD = 3.3 V/5.5 V
VDD = 3.3 V/5.5 V, 400 kHz fSCL
VDD = 3.3 V/5.5 V, 3.4 MHz fSCL
VDD = 3.3 V/5.5 V, 400 kHz fSCL
VDD = 3.3 V/5.5 V, 3.4 MHz fSCL
VDD = 3.3 V/5.5 V, 400 kHz fSCL
VDD = 3.3 V/5.5 V, 3.4 MHz fSCL Mode1
VDD = 3.3 V/5.5 V, 3.4 MHz fSCL Mode 2
VDD = 3.3 V/5.5 V
0.495/2.2
1.98/6.05
2.31/7.7
3.3/11
mW max
mW max
mW typ
µW max
VDD = 3.3 V/5.5 V, 400 kHz fSCL
VDD = 3.3 V/5.5 V, 3.4 MHz fSCL Mode 1
VDD = 3.3 V/5.5 V, 3.4 MHz fSCL Mode 2
VDD = 3.3 V/5.5 V
1 Maximum/minimum ac dynamic performance, INL and DNL specifications are typical specifications when operating in Mode 2 with I2C high speed mode SCL
frequencies. Specifications outlined for Mode 2 apply to Mode 3 also. Sample delay and bit trial delay enabled.
2 See the Terminology section.
3 Guaranteed by initial characterization.
Rev. 0 | Page 4 of 28
Free Datasheet http://www.datasheetlist.com/
5 Page 
AD7992
TYPICAL PERFORMANCE CHARACTERISTICS
0
FS = 121kSPS
FSCL = 3.4MHz
–20
FIN = 10kHz
SNR = 71.84dB
SINAD = 71.68dB
THD = –86.18dB
–40 SFDR = –88.70dB
–60
–80
–100
–120
0
20 40
FREQUENCY (kHz)
60
Figure 4. Dynamic Performance with 5 V Supply and 2.5 V Reference,
121 kSPS, Mode 1, Single-Channel Mode
0
SNR = 73.23dB
SINAD = 73.10dB
THD = –88.59dB
–20 SFDR = –90.46dB
FS = 121kSPS
FSCL = 3.4MHz
–40 FIN = 10kHz
–60
–80
–100
–120
0
10 20 30 40 50 60
FREQUENCY (kHz)
Figure 5. Dynamic Performance with 5.5 V Supply and 5.5 V Reference,
121 KSPS, Mode 1, Dual-Channel Mode
100
90
VDD = 3V
80
VDD = 5V
70
60
50
40
30
20
10
VDD = 3V/5V
200mV p-p SINE WAVE
ON VDD
2nF CAPACITOR ON VDD
100 1000
SUPPLY-RIPPLE FREQUENCY (kHz)
Figure 6. PSRR vs. Supply-Ripple Frequency, Single-Channel Mode Only
76
74
VDD = 5.5V
72
VDD = 2.7V
70
68
66
64
62
60
1
VDD = 5.0V VDD = 4.5V
VDD = 3.0V
VDD = 3.3V
10
INPUT FREQUENCY kHz
VREF = VDD
100
Figure 7. SINAD vs. Analog Input Frequency for Various Supply Voltages at
136 kSPS with 3.4 MHz fSCL
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
500 1000 1500 2000 2500 3000 3500 4000
CODE
Figure 8. Typical INL, VDD = 5.5 V, Reference = 2.5 V, Mode 1,
3.4 MHz fSCL , 121 kSPS
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
500 1000 1500 2000 2500 3000 3500 4000
CODE
Figure 9. Typical DNL, VDD = 5.5 V, Reference = 2.5 V Mode 1,
3.4 MHz fSCL , 121 kSPS
Rev. 0 | Page 10 of 28
Free Datasheet http://www.datasheetlist.com/
11 Page | ||
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