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Teilenummer | 89170M |
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Beschreibung | LC89170M | |
Hersteller | Sanyo Semicon Device | |
Logo | ||
Gesamt 8 Seiten Ordering number : EN*5536A
CMOS LSI
LC89170M
CD Player Text Data IC
Preliminary
Overview
The LC89170M is an IC that decodes the text data, such
as song names, stored in subcode channels R to W of a
compact disk’s read-in area.
Features
• Accepts the channel R to W subcode data through a
subcode interface.
• Can continuously output the channel R to W data for
each 1PACK24 symbol.
• Performs error detection (cyclic redundancy code) and
outputs both the data and the result of that check.
• Provides synchronization protection for the subcode
interface.
• Supports low-voltage operation (3.3 V)
• Provided in the miniature MFP-14S package.
Package Dimensions
unit: mm
3111-MFP14S
[LC89170M]
SANYO: MFP14S
Specifications
Absolute Maximum Ratings at Ta = 25 °C, VSS = 0 V
Parameter
Maximum supply voltage
I/O voltages
Input current
Operating temperature
Storage temperature
Symbol
VDD max
VI VO
II
Topr
Tstg
Conditions
Recommended Operating Conditions at Ta = 25 °C, VSS = 0 V
Parameter
Supply voltage
Operating temperature
Symbol
VDD
Topr
Conditions
Ratings
–0.3 to +7.0
–0.3 to VDD + 0.3
±10
–30 to +70
–55 to +125
Unit
V
V
mA
°C
°C
Ratings
Unit
min typ max
3.0 5.0 5.5 V
–30 +70 V
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
93096HA (OT) No. 5536-1/8
Free Datasheet http://www.datasheetlist.com/
LC89170M
The EXCK clock characteristics are determined by SW2 as listed in the table below.
EXCK Clock Selection by SW2
SW1
SW2
tCD
tWH
tWL Unit
12.28
1.89
1.89
µs
[L] [L]
208TMCK
32TMCK
32TMCK
µs
18.90
7.56
7.56
µs
[L] [H]
320TMCK
128TMCK
128TMCK
µs
The upper boxes assume MCK = 16.934 MHz
The lower boxes indicate the relationship with MCK (TMCK = 1/MCK)
• Microcontroller interface
The LC89170M includes a 32-word × 8-bit dual-port RAM on chip, and the 1PACK 24 symbols from subcode channels
R to W can be read out once every 3.3 ms (or once every 1.66 for double-speed playback) over the microcontroller
interface. Figure 3 shows the timing.
Figure 3 Microcontroller Interface Output Timing
The 1PACK 24 symbols for the subcode R to W data (18 bytes) are entered into the dual-port RAM and input to the CRC
checking circuit. After the data for 1 PACK has all been input, a falling edge is output from the DQSY pin and the CRC
flags are output from SRDT. A high is output for the CRC flags if the check returned OK. Next, 128 bits of data are
output by inputting the SCLK clock signal. A single packet of data is output by repeating this operation four times.
No. 5536-6/8
Free Datasheet http://www.datasheetlist.com/
6 Page | ||
Seiten | Gesamt 8 Seiten | |
PDF Download | [ 89170M Schematic.PDF ] |
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