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DS312 Schematic ( PDF Datasheet ) - Xilinx

Teilenummer DS312
Beschreibung Spartan-3E FPGA Family
Hersteller Xilinx
Logo Xilinx Logo 




Gesamt 30 Seiten
DS312 Datasheet, Funktion
1
DS312 July 19, 2013
Module 1:
Introduction and Ordering Information
DS312 (v4.1) July 19, 2013
• Introduction
• Features
• Architectural Overview
• Package Marking
• Ordering Information
Module 2:
Functional Description
DS312 (v4.1) July 19, 2013
• Input/Output Blocks (IOBs)
• Overview
• SelectIO™ Signal Standards
• Configurable Logic Block (CLB)
• Block RAM
• Dedicated Multipliers
• Digital Clock Manager (DCM)
• Clock Network
• Configuration
• Powering Spartan®-3E FPGAs
• Production Stepping
Spartan-3E FPGA Family
Data Sheet
Product Specification
Module 3:
DC and Switching Characteristics
DS312 (v4.1) July 19, 2013
• DC Electrical Characteristics
• Absolute Maximum Ratings
• Supply Voltage Specifications
• Recommended Operating Conditions
• DC Characteristics
• Switching Characteristics
• I/O Timing
• SLICE Timing
• DCM Timing
• Block RAM Timing
• Multiplier Timing
• Configuration and JTAG Timing
Module 4:
Pinout Descriptions
DS312 (v4.1) July 19, 2013
• Pin Descriptions
• Package Overview
• Pinout Tables
• Footprint Diagrams
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DS312 July 19, 2013
Product Specification
www.xilinx.com
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DS312 Datasheet, Funktion
Spartan-3E FPGA Family: Introduction and Ordering Information
Ordering Information
Spartan-3E FPGAs are available in both standard and
Pb-free packaging options for all device/package
combinations. All devices are available in Pb-free packages,
which adds a ‘G’ character to the ordering code. All devices
are available in either Commercial (C) or Industrial (I)
temperature ranges. Both the standard –4 and faster –5
speed grades are available for the Commercial temperature
range. However, only the –4 speed grade is available for the
Industrial temperature range. See Table 2 for valid
device/package combinations.
Example: XC3S250E -4 FT 256 C S1 (optional code to specify Stepping 1)
Device Type
Speed Grade
Temperature Range
Package Type
Number of Pins
DS312_03_082409
Device
XC3S100E
Speed Grade
-4 Standard Performance
XC3S250E -5 High Performance(1)
XC3S500E(2)
XC3S1200E
XC3S1600E
VQ100
VQG100
CP132
CPG132
TQ144
TQG144
PQ208
PQG208
FT256
FTG256
FG320
FGG320
FG400
FGG400
FG484
FGG484
Package Type / Number of Pins
100-pin Very Thin Quad Flat Pack (VQFP)
Temperature Range (TJ)
C Commercial (0°C to 85°C)
132-ball Chip-Scale Package (CSP)
I Industrial (–40°C to 100°C)
144-pin Thin Quad Flat Pack (TQFP)
208-pin Plastic Quad Flat Pack (PQFP)
256-ball Fine-Pitch Thin Ball Grid Array (FTBGA)
320-ball Fine-Pitch Ball Grid Array (FBGA)
400-ball Fine-Pitch Ball Grid Array (FBGA)
484-ball Fine-Pitch Ball Grid Array (FBGA)
Notes:
1. The -5 speed grade is exclusively available in the Commercial temperature range.
2. The XC3S500E VQG100 is available only in the -4 Speed Grade.
3. See DS635 for the XA Automotive Spartan-3E FPGAs.
Production Stepping
The Spartan-3E FPGA family uses production stepping to
indicate improved capabilities or enhanced features.
Stepping 1 is, by definition, a functional superset of
Stepping 0. Furthermore, configuration bitstreams
generated for any stepping are forward compatible. See
Table 72 for additional details.
Xilinx has shipped both Stepping 0 and Stepping 1. Designs
operating on the Stepping 0 devices perform similarly on a
Stepping 1 device. Stepping 1 devices have been shipping
since 2006. The faster speed grade (-5), Industrial (I grade),
Automotive devices, and -4C devices with date codes 0901
(2009) and later, are always Stepping 1 devices. Only -4C
devices have shipped as Stepping 0 devices.
To specify only the later stepping for the -4C, append an S#
suffix to the standard ordering code, where # is the stepping
number, as indicated in Table 3.
Table 3: Spartan-3E Optional Stepping Level Ordering
Stepping
Number
Suffix Code
Status
0 None or S0
Production
1 S1
Production
The stepping level is optionally marked on the device using
a single number character, as shown in Figure 2, Figure 3,
and Figure 4.
DS312 (v4.1) July 19, 2013
Product Specification
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DS312 pdf, datenblatt
Spartan-3E FPGA Family: Functional Description
Input Delay Functions
Each IOB has a programmable delay block that optionally
delays the input signal. In Figure 6, the signal path has a
coarse delay element that can be bypassed. The input
signal then feeds a 6-tap delay line. The coarse and tap
delays vary; refer to timing reports for specific delay values.
All six taps are available via a multiplexer for use as an
asynchronous input directly into the FPGA fabric. In this
way, the delay is programmable in 12 steps. Three of the six
taps are also available via a multiplexer to the D inputs of
the synchronous storage elements. The delay inserted in
the path to the storage element can be varied in six steps.
The first, coarse delay element is common to both
asynchronous and synchronous paths, and must be either
used or not used for both paths.
The delay values are set up in the silicon once at
configuration time—they are non-modifiable in device
operation.
The primary use for the input delay element is to adjust the
input delay path to ensure that there is no hold time
requirement when using the input flip-flop(s) with a global
clock. The default value is chosen automatically by the
Xilinx software tools as the value depends on device size
and the specific device edge where the flip-flop resides. The
value set by the Xilinx ISE software is indicated in the Map
X-Ref Target - Figure 6
report generated by the implementation tools, and the
resulting effects on input timing are reported using the
Timing Analyzer tool.
If the design uses a DCM in the clock path, then the delay
element can be safely set to zero because the
Delay-Locked Loop (DLL) compensation automatically
ensures that there is still no input hold time requirement.
Both asynchronous and synchronous values can be
modified, which is useful where extra delay is required on
clock or data inputs, for example, in interfaces to various
types of RAM.
These delay values are defined through the
IBUF_DELAY_VALUE and the IFD_DELAY_VALUE
parameters. The default IBUF_DELAY_VALUE is 0,
bypassing the delay elements for the asynchronous input.
The user can set this parameter to 0-12. The default
IFD_DELAY_VALUE is AUTO. IBUF_DELAY_VALUE and
IFD_DELAY_VALUE are independent for each input. If the
same input pin uses both registered and non-registered
input paths, both parameters can be used, but they must
both be in the same half of the total delay (both either
bypassing or using the coarse delay element).
IFD_DELAY_VALUE
Synchronous input (IQ1)
DQ
Synchronous input (IQ2)
DQ
Coarse Delay
PAD
Asynchronous input (I)
IBUF_DELAY_VALUE
UG331_c10_09_011508
Figure 6: Programmable Fixed Input Delay Elements
DS312 (v4.1) July 19, 2013
Product Specification
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