PDF AD9914 Data sheet ( Hoja de datos )

Número de pieza	AD9914
Descripción	3.5 GSPS Direct Digital Synthesizer
Fabricantes	Analog Devices
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No Preview Available ! Data Sheet FEATURES 3.5 GSPS internal clock speed Integrated 12-bit DAC Frequency tuning resolution to 190 pHz 16-bit phase tuning resolution 12-bit amplitude scaling Programmable modulus Automatic linear and nonlinear frequency sweeping capability 32-bit parallel datapath interface 8 frequency/phase offset profiles Phase noise: −128 dBc/Hz (1 kHz offset at 1396 MHz) Wideband SFDR < −50 dBc Serial or parallel I/O control 3.5 GSPS Direct Digital Synthesizer with 12-Bit DAC AD9914 1.8 V/3.3 V power supplies Software and hardware controlled power-down 88-lead LFCSP package PLL REF CLK multiplier Phase modulation capability Amplitude modulation capability APPLICATIONS Agile LO frequency synthesis Programmable clock generator FM chirp source for radar and scanning systems Test and measurement equipment Acousto-optic device drivers Polar modulator Fast frequency hopping FUNCTIONAL BLOCK DIAGRAM AD9914 HIGH SPEED PARALLEL MODULATION PORT LINEAR SWEEP BLOCK 3.5GSPS DDS CORE 12-BIT DAC REF CLK MULTIPLIER TIMING AND CONTROL SERIAL OR PARALLEL DATA PORT Figure 1. Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2012–2014 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com Free Datasheet http://www.datasheet-pdf.com/ 1 page Data Sheet AD9914 AC SPECIFICATIONS AVDD (1.8V) and DVDD (1.8V) = 1.8 V ± 5%, AVDD3 (3.3V) and DVDD_I/O (3.3V) = 3.3 V ± 5%, TA = 25°C, RSET = 3.3 kΩ, IOUT = 20 mA, external reference clock frequency = 3.5 GHz with reference clock (REF CLK) multiplier bypassed, unless otherwise noted. Table 2. Parameter REF CLK INPUT REF CLK Multiplier Bypassed Input Frequency Range Duty Cycle Minimum Differential Input Level System Clock (SYSCLK) PLL Enabled VCO Frequency Range VCO Gain (KV) Maximum PFD Rate CLOCK DRIVERS SYNC_CLK Output Driver Frequency Range Duty Cycle Rise Time/Fall Time (20% to 80%) SYNC_OUT Output Driver Frequency Range Duty Cycle Rise Time (20% to 80%) Fall Time (20% to 80%) DAC OUTPUT CHARACTERISTICS Output Frequency Range (1st Nyquist Zone) Output Resistance Min 500 45 632 2400 45 33 0 Output Capacitance Full-Scale Output Current Gain Error Output Offset Voltage Compliance Range Wideband SFDR −10 AVDD − 0.50 101.1 MHz Output 427.5 MHz Output 696.5 MHz Output 1396.5 MHz Output Narrow-Band SFDR 100.5 MHz Output 427.5 MHz Output 696.5 MHz Output 1396.5 MHz Output DIGITAL TIMING SPECIFICATIONS Time Required to Enter Power-Down Time Required to Leave Power-Down Minimum Master Reset time Maximum DAC Calibration Time (tCAL) 24 Maximum PLL Calibration Time (tREF_CLK) Maximum Profile Toggle Rate Typ Max Unit 3500 55 2500 60 125 MHz % mV p-p MHz MHz/V MHz Test Conditions/Comments Input frequency range Maximum fOUT is 0.4 × fSYSCLK Equivalent to 316 mV swing on each leg 146 50 55 650 1350 1670 9.1 66 MHz % ps MHz % ps ps 10 pF load CFR2 register, Bit 9 = 1 10 pF load 10 pF load 1750 MHz 50 Ω 1 pF 20.48 mA +10 % FS 0.6 μA AVDD + 0.50 V −66 dBc −65 dBc −57 dBc −52 dBc −95 dBc −95 dBc −95 dBc −92 dBc Single-ended (each pin internally terminated to AVDD (3.3V)) Range depends on DAC RSET resistor See the Typical Performance Characteristics section 0 MHz to 1750 MHz 0 MHz to 1750 MHz 0 MHz to 1750 MHz 0 MHz to 1750 MHz See the Typical Performance Characteristics section ±500 kHz ±500 kHz ±500 kHz ±500 kHz 45 250 135 16 8 2 ns ns SYSCLK cycles µs ms ms SYNC_CLK period Power-down mode loses DAC/PLL calibration settings Must recalibrate DAC/PLL See the DAC Calibration Output section for formula PFD rate = 25 MHz PFD rate = 50 MHz Rev. D \| Page 5 of 48 Free Datasheet http://www.datasheet-pdf.com/ 5 Page Data Sheet AD9914 Pin No. 67 82 Mnemonic EXT_PWR_DWN SYNC_CLK 85 MASTER_RESET 86 I/O_UPDATE EPAD 1 I = input, O = output. I/O1 Description I External Power-Down. Digital input (active high). A high level on this pin initiates the currently programmed power-down mode. O Clock Output. Digital output. Many of the digital inputs on the chip, such as I/O_UPDATE, PS[2:0], and the parallel data port (D0 to D31), must be set up on the rising edge of this signal. I Master Reset. Digital input (active high). Clears all memory elements and sets registers to default values. I Input/Output Update. Digital input (active high). A high on this pin transfers the contents of the I/O buffers to the corresponding internal registers. Exposed Pad. The EPAD must be soldered to ground. Rev. D \| Page 11 of 48 Free Datasheet http://www.datasheet-pdf.com/ 11 Page

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