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PDF EPCQ128 Data sheet ( Hoja de datos )
| Número de pieza | EPCQ128 | |
| Descripción | Quad-Serial Configuration (EPCQ) Devices | |
| Fabricantes | Altera Corporation | |
| Logotipo |  |
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Quad-Serial Configuration (EPCQ) Devices
Datasheet
CF52012-3.0
Datasheet
This datasheet describes quad-serial configuration (EPCQ) devices.
Supported Devices
Table 1 lists the supported Altera EPCQ devices.
Table 1. Altera EPCQ Devices
Device
Memory Size
(bits)
EPCQ16
EPCQ32
EPCQ64
EPCQ128
EPCQ256
16,777,216
33,554,432
67,108,864
134,217,728
268,435,456
On-Chip Decompression
Support
ISP Support
No Yes
No Yes
No Yes
No Yes
No Yes
Cascading
Support
No
No
No
No
No
Recommended
Reprogrammable Operating
Voltage (V)
Yes 3.3
Yes 3.3
Yes 3.3
Yes 3.3
Yes 3.3
Features
EPCQ devices offer the following features:
■ Serial or quad-serial FPGA configuration in devices that support active serial
(AS) x1 or AS x4 configuration schemes
■ Low cost, low pin count, and non-volatile memory
■ 2.7-V to 3.6-V operation
■ Available in 8- and 16-pin small-outline integrated circuit (SOIC) package
■ Reprogrammable memory with more than 100,000 erase or program cycles
■ Write protection support for memory sectors using status register bits
■ Fast read, extended dual input fast read, and extended quad input fast read of the
entire memory using a single operation code
■ Write bytes, extended dual input fast write bytes, and extended quad input fast
write bytes of the entire memory using a single operation code
■ Reprogrammable with an external microprocessor using the SRunner software
driver
■ In-system programming (ISP) support with the SRunner software driver
■ ISP support with USB-Blaster, EthernetBlaster II, or EthernetBlaster download
cables
101 Innovation Drive
San Jose, CA 95134
www.altera.com
© 2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS,
QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark
Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their
respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor
products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use
of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are
advised to obtain the latest version of device specifications before relying on any published information and before placing orders
for products or services.
ISO
9001:2008
Registered
July 2012 Altera Corporation
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1 page  
Memory Array Organization
Page 5
Table 5. Address Range for Sectors 127..0 and Subsectors 2047..0 in EPCQ64 Devices
—Preliminary (Part 2 of 2)
Sector
Subsector
Address Range (Byte Addresses in HEX)
Start
End
1023
1022
...
63
1010
1009
1008
1007
1006
...
62
994
993
992
31
30
...
1
18
17
16
15
14
...
0
2
1
0
3FF000
3FE000
...
3F2000
3F1000
3F0000
3EF000
3EE000
...
3E2000
3E1000
3E0000
1F000
1E000
...
12000
11000
10000
F000
E000
...
2000
1000
H’0000000
3FFFFF
3FEFFF
...
3F2FFF
3F1FFF
3F0FFF
3EFFFF
3EEFFF
...
3E2FFF
3E1FFF
3E0FFF
1FFFF
1EFFF
...
12FFF
11FFF
10FFF
FFFF
EFFF
...
2FFF
1FFF
H’0000FFF
July 2012 Altera Corporation
Quad-Serial Configuration (EPCQ) Devices Datasheet
Free Datasheet http://www.datasheet-pdf.com/
5 Page 
Memory Operations
Page 11
Memory Operations
This section describes the operations that you can use to access the memory in EPCQ
devices. When performing the operation, addresses and data are shifted in and out of
the device serially, with the MSB first.
Timing Requirements
When the active low chip select (nCS) signal is driven low, shift in the operation code
into the EPCQ device using the serial data (DATA) pin. Each operation code bit is
latched into the EPCQ device on the rising edge of the DCLK.
While executing an operation, shift in the desired operation code, followed by the
address or data bytes as listed in Table 8. The device must drive the nCS pin high after
the last bit of the operation sequence is shifted in.
For read operations, the data read is shifted out on the DATA pin. You can drive the nCS
pin high when any bit of the data is shifted out.
For write and erase operations, drive the nCS pin high at a byte boundary, that is in a
multiple of eight clock pulses. Otherwise, the operation is rejected and not executed.
All attempts to access the memory contents while a write or erase cycle is in progress
are rejected, and the write or erase cycle continues unaffected.
Addressing Mode
The 3-byte addressing mode is enabled by default. To access the EPCQ256 memory,
you must use the 4-byte addressing mode. In 4-byte addressing mode, the address
width is 32-bit address. To enable the 4-byte addressing mode, you must execute the
4BYTEADDREN operation. This addressing mode takes effect immediately after you
execute the 4BYTEADDREN operation and remains active in the subsequent
power-ups. To disable the 4-byte addressing mode, you must execute the
4BYTEADDREX operation.
1 If you are using the Quartus II software or the SRunner software to program the
EPCQ256 device, you do not need to execute the 4BYTEADDREN operation. These
software automatically enable the 4-byte addressing mode when programming the
device.
July 2012 Altera Corporation
Quad-Serial Configuration (EPCQ) Devices Datasheet
Free Datasheet http://www.datasheet-pdf.com/
11 Page | ||
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