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EPCQ16 Schematic ( PDF Datasheet ) - Altera Corporation

Teilenummer EPCQ16
Beschreibung Quad-Serial Configuration (EPCQ) Devices
Hersteller Altera Corporation
Logo Altera Corporation Logo 




Gesamt 42 Seiten
EPCQ16 Datasheet, Funktion
Quad-Serial Configuration (EPCQ) Devices
Datasheet
CF52012-3.0
Datasheet
This datasheet describes quad-serial configuration (EPCQ) devices.
Supported Devices
Table 1 lists the supported AlteraEPCQ devices.
Table 1. Altera EPCQ Devices
Device
Memory Size
(bits)
EPCQ16
EPCQ32
EPCQ64
EPCQ128
EPCQ256
16,777,216
33,554,432
67,108,864
134,217,728
268,435,456
On-Chip Decompression
Support
ISP Support
No Yes
No Yes
No Yes
No Yes
No Yes
Cascading
Support
No
No
No
No
No
Recommended
Reprogrammable Operating
Voltage (V)
Yes 3.3
Yes 3.3
Yes 3.3
Yes 3.3
Yes 3.3
Features
EPCQ devices offer the following features:
Serial or quad-serial FPGA configuration in devices that support active serial
(AS) x1 or AS x4 configuration schemes
Low cost, low pin count, and non-volatile memory
2.7-V to 3.6-V operation
Available in 8- and 16-pin small-outline integrated circuit (SOIC) package
Reprogrammable memory with more than 100,000 erase or program cycles
Write protection support for memory sectors using status register bits
Fast read, extended dual input fast read, and extended quad input fast read of the
entire memory using a single operation code
Write bytes, extended dual input fast write bytes, and extended quad input fast
write bytes of the entire memory using a single operation code
Reprogrammable with an external microprocessor using the SRunner software
driver
In-system programming (ISP) support with the SRunner software driver
ISP support with USB-Blaster, EthernetBlaster II, or EthernetBlaster download
cables
101 Innovation Drive
San Jose, CA 95134
www.altera.com
© 2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS,
QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark
Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their
respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor
products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use
of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are
advised to obtain the latest version of device specifications before relying on any published information and before placing orders
for products or services.
ISO
9001:2008
Registered
July 2012 Altera Corporation
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EPCQ16 Datasheet, Funktion
Page 6
Memory Array Organization
Address Range for EPCQ128
Table 6 lists the address range for each sector in EPCQ128 devices.
Table 6. Address Range for Sectors 255..0 and Subsectors 4095..0 in EPCQ128 Devices
—Preliminary (Part 1 of 2)
Sector
255
254
129
128
127
Subsector
4095
4094
...
4082
4081
4080
4079
4078
...
4066
4065
4064
2079
2078
...
2066
2065
2064
2063
2062
...
2050
2049
2048
2047
2046
...
2034
2033
2032
Address Range (Byte Addresses in HEX)
Start
End
FFF000
FFE000
...
FF2000
FF1000
FF0000
FEF000
FEE000
...
FE2000
FE1000
FE0000
81F000
81E000
...
812000
811000
810000
80F000
80E000
...
802000
801000
800000
7FF000
7FE000
...
7F2000
7F1000
7F0000
FFFFFF
FFEFFF
...
FF2FFF
FF1FFF
FF0FFF
FEFFFF
FEEFFF
...
FE2FFF
FE1FFF
FE0FFF
81FFFF
81EFFF
...
812FFF
811FFF
810FFF
80FFFF
80EFFF
...
802FFF
801FFF
800FFF
7FFFFF
7FEFFF
...
7F2FFF
7F1FFF
7F0FFF
Quad-Serial Configuration (EPCQ) Devices Datasheet
July 2012 Altera Corporation
Free Datasheet http://www.datasheet-pdf.com/

6 Page









EPCQ16 pdf, datenblatt
Page 12
Memory Operations
Summary of Operation Codes
Table 8 lists the supported operations.
Table 8. Operation Codes for EPCQ Devices—Preliminary
Operation
Read status
Read bytes
Read device identification
Fast read
Extended dual input fast
read
Extended quad input fast
read
Write enable
Write disable
Write status
Write bytes
Extended dual input fast
write bytes
Extended quad input fast
write bytes
Erase bulk
Erase sector
4BYTEADDREN (6)
4BYTEASSREX (6)
Operation Code (1)
b’0000 0101
b’0000 0011
b’1001 111x
b’0000 1011
b’1011 1011
Address Bytes
0
3 or 4
0
3 or 4
Dummy Bytes
0
0
0
8 (5)
Data Bytes
1 to infinite (3)
1 to infinite (3)
1 to 20 (3)
1 to infinite (3)
DCLK fMAX (MHz) (2)
100
50
100
100
3 or 4
8 (5) 1 to infinite (3)
100
b’1110 1011
b’0000 0110
b’0000 0100
b’0000 0001
b’0000 0010
b’1101 0010
3 or 4
0
0
0
3 or 4
3 or 4
10 (5)
0
0
0
0
0
1 to infinite (3)
0
0
1
1 to 256 (4)
1 to 256 (4)
100
100
100
100
100
100
b’0001 0010
b’1100 0111
b’1101 1000
b’1011 0111
b’1110 1001
3 or 4
0
3 or 4
0
0
0 1 to 256 (4)
00
00
00
00
100
100
100
100
100
Notes to Table 8:
(1) List MSB first and LSB last.
(2) Pending characterization data.
(3) The status register, data, or read device identification is read out at least once on the DATA1 pin and is continuously read out until the nCS pin is
driven high.
(4) A write bytes operation requires at least one data byte on the DATA1 pin. If more than 256 bytes are sent to the device, only the last 256 bytes are
written to the memory.
(5) You can configure the number of dummy bytes.
(6) This operation is applicable for EPCQ256 device only.
Quad-Serial Configuration (EPCQ) Devices Datasheet
July 2012 Altera Corporation
Free Datasheet http://www.datasheet-pdf.com/

12 Page





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