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PDF ADSP21161 Data sheet ( Hoja de datos )
| Número de pieza | ADSP21161 | |
| Descripción | SHARC Processor Hardware Reference | |
| Fabricantes | Analog Devices | |
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Hay una vista previa y un enlace de descarga de ADSP21161 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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ADSP-21161 SHARC® Processor
Hardware Reference
Analog Devices, Inc.
One Technology Way
Norwood, Mass. 02062-9106
Revision 4.0, February 2005
Part Number
82-001944-01
Free Datasheet http://www.datasheet4u.net/
1 page  
CONTENTS
Multiplier (Fixed-Point) Result Register ................................. 2-16
Multiplier Status Flags ........................................................... 2-19
Multiplier Instruction Summary ............................................ 2-20
Barrel-Shifter (Shifter) ................................................................. 2-23
Shifter Operation .................................................................. 2-23
Shifter Status Flags ................................................................ 2-27
Shifter Instruction Summary .................................................. 2-28
Data Register File ........................................................................ 2-30
Alternate (Secondary) Data Registers ........................................... 2-32
Multifunction Computations ...................................................... 2-34
Secondary Processing Element (PEy) ............................................ 2-37
Dual Compute Units Sets ...................................................... 2-39
Dual Register Files ................................................................. 2-42
Dual Alternate Registers ........................................................ 2-43
SIMD (Computational) Operations ....................................... 2-43
SIMD And Status Flags ......................................................... 2-46
PROGRAM SEQUENCER
Instruction Pipeline ...................................................................... 3-7
Instruction Cache ......................................................................... 3-8
Using the Cache .................................................................... 3-11
Optimizing Cache Usage ....................................................... 3-11
Branches and Sequencing ............................................................ 3-13
Conditional Branches ............................................................ 3-15
Delayed Branches .................................................................. 3-15
ADSP-21161 SHARC Processor Hardware Reference
v
Free Datasheet http://www.datasheet4u.net/
5 Page 
CONTENTS
32- to 48-Bit Packing Address Generation Scheme ............... 5-109
Total Program Size (32- to 48-Bit Packing) ...................... 5-110
16- to 48-Bit Packing Address Generation Scheme ............... 5-111
Total Program Size (16- to 48-Bit Packing) ...................... 5-111
8- to 48-Bit Packing Address Generation Scheme ................. 5-112
Total Program Size (8- to 48-Bit Packing) ........................ 5-113
No Packing (48- to 48-Bit) Address Generation Scheme ....... 5-113
I/O PROCESSOR
DMA Channel Allocation and Priorities ...................................... 6-16
DMA Interrupt Vector Locations ................................................. 6-18
Booting Modes ........................................................................... 6-20
DMA Controller Operation ........................................................ 6-20
Managing DMA Channel Priority .......................................... 6-22
Chaining DMA Processes ...................................................... 6-25
Transfer Control Block (TCB) Chain Loading ................... 6-26
Setting Up and Starting the Chain ..................................... 6-28
Inserting a TCB in an Active Chain ................................... 6-28
External Port DMA ..................................................................... 6-29
External Port Registers ........................................................... 6-30
External Port FIFO Buffers .................................................... 6-33
External Port DMA Data Packing .......................................... 6-34
32-Bit Bus Downloading ................................................... 6-37
16-Bit Bus Downloading ................................................... 6-38
8-Bit Bus Downloading ..................................................... 6-39
ADSP-21161 SHARC Processor Hardware Reference
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Free Datasheet http://www.datasheet4u.net/
11 Page | ||
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| PDF Descargar | [ Datasheet ADSP21161.PDF ] | |
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