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PDF ADP1972 Data sheet ( Hoja de datos )
| Número de pieza | ADP1972 | |
| Descripción | PWM Controller | |
| Fabricantes | Analog Devices | |
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Data Sheet
FEATURES
Input voltage range: 6 V to 60 V
On-board 5 V low dropout regulator
Selective buck or boost mode
Excellent PWM linearity with high amplitude PWM sawtooth
4.0 V p-p
FAULT input compatible with AD8450
COMP input compatible with AD8450
Adjustable frequency from 50 kHz to 300 kHz
Synchronization output or input with adjustable phase shift
Programmable maximum duty cycle
Maximum internal duty cycle: 98%
Programmable soft start
Peak hiccup current limit protection
Input voltage UVLO protection
TSD protection
16-lead TSSOP
APPLICATIONS
PWM battery test systems with recycle capability including
hybrid vehicles, PCs, and camera batteries
Compatible with AD8450 constant voltage (CV) and constant
current (CC) monitors
Buck or Boost, PWM Controller
for Battery Test Solutions
ADP1972
GENERAL DESCRIPTION
The ADP1972 is a constant frequency, voltage mode, pulse-width
modulation (PWM) controller for buck or boost, dc-to-dc,
asynchronous applications. The ADP1972 is designed for use in
asynchronous battery testing applications with an external, high
voltage field effect transistor (FET), half bridge driver, and an
external control device, such as the AD8450. The asynchronous
device operates as a buck converter in battery charge mode and
operates as a boost converter in recycle mode to recycle energy
to the input bus.
The ADP1972 high voltage, VIN supply pin can withstand a
maximum operating voltage of 60 V and reduces the need for
additional system supply voltages. The ADP1972 has integrated
features such as precision enable, pin selective buck or boost
mode operation, internal and external synchronization control
with programmable phase shift, programmable maximum duty
cycle, and programmable peak hiccup current limit. Additional
protection features include soft start to limit input inrush
current during startup, input voltage undervoltage lockout
(UVLO), and thermal shutdown (TSD). The ADP1972 also has
a COMP pin to provide external control of the PWM operation
and a FAULT pin that can be signaled to disable the DH and DL
outputs if a fault condition occurs externally to the ADP1972.
The ADP1972 is available in a 16-lead TSSOP package.
TYPICAL APPLICATION CIRCUIT
24V
VIN
VREG
SYNC
SCFG
24V RECYLCING
DC BUS
FROM
CENTRAL PC
FROM
ANALOG IC
MODE
DH
EN
ADP1972
COMP
DL
FAULT
CL
FREQ
DMAX
GNDSENSE
GND
SS
HV
MOSFET
DRIVER
Figure 1.
Rev. 0
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2014 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
Free Datasheet http://www.datasheet4u.net/
1 page  
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
VIN, EN, FAULT to GND
SYNC, COMP, MODE to GND
DH, DL, SS, DMAX, SCFG, CL to GND
GNDSENSE to GND
Operating Ambient Temperature Range
Junction Temperature
Storage Temperature Range
Rating
−0.3 V to +61 V
−0.3 V to +5.5 V
−0.3 V to VREG + 0.3 V
−0.3 V to +0.3 V
−40°C to +85°C
125°C
−65°C to +150°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Absolute maximum ratings apply individually only, not in
combination.
THERMAL OPERATING RANGES
The ADP1972 can be damaged when the junction temperature
limits are exceeded. The maximum operating junction
temperature (TJ MAX) takes precedence over the maximum
operating ambient temperature (TA MAX). Monitoring ambient
temperature does not guarantee that the junction temperature
(TJ) is within the specified temperature limits.
ADP1972
In applications with high power dissipation and poor printed
circuit board (PCB) thermal resistance, the maximum ambient
temperature may need to be derated. In applications with
moderate power dissipation and low PCB thermal resistance,
the maximum ambient temperature can exceed the maximum
limit when the junction temperature is within specification
limits.
The junction temperature (TJ) of the device is dependent on the
ambient temperature (TA), the power dissipation of the device
(PD), and the junction to ambient thermal resistance of the
package (θJA). Use the following equation to calculate the
maximum junction temperature (TJ) from the ambient
temperature (TA) and power dissipation (PD):
TJ = TA + (PD × θJA)
(1)
For additional information on thermal resistance, refer to
Application Note AN-000, Thermal Characteristics of IC
Assembly.
ESD CAUTION
Rev. 0 | Page 5 of 20
Free Datasheet http://www.datasheet4u.net/
5 Page 
Data Sheet
ADP1972
EN/SHUTDOWN
The EN input turns the ADP1972 on or off. The EN pin of the
ADP1972 can operate from voltages up to 60 V and is designed
with stable ±20% thresholds for precision enable control. When
the EN voltage is less than 1.22 V (typical), the ADP1972 shuts
down, driving both DL and DH low. When the ADP1972 is shut
down, the VIN supply current is 15 µA (typical). When the EN
voltage is greater than 1.25 V (typical), the ADP1972 is enabled.
The device can be disabled via the EN pin, a fault condition
indicated by a TSD event, a UVLO condition, or an external
fault condition signaled via the FAULT pin.
UNDERVOLTAGE LOCKOUT (UVLO)
There is internal UVLO for the VIN pin. When VIN rises, the
UVLO does not allow the ADP1972 to turn on unless VIN is
greater than 5.71 V (typical). When VIN falls, the UVLO
disables the device when VIN drops below 5.34 V (typical). The
UVLO prevents potentially erratic operation of the application
at low input voltages that may damage the ADP1972 and the
external circuitry. The UVLO levels have ~370 mV of hysteresis
to ensure glitch free startup.
SOFT START
The ADP1972 is equipped with a programmable soft start that
prevents output voltage overshoot during startup. When the
ADP1972 is enabled with the EN pin, the VREG voltage begins
rising to 5 V. When VREG reaches 90% of its 5 V (typical)
value, the 5 µA (typical) internal soft start current (ISS) begins
charging the soft start capacitor (CSS), causing the voltage on the
SS pin (VSS) to rise. While VSS is less than 0.52 V (typical), the
ADP1972 switching control remains disabled.
When VSS reaches 0.52 V (typical), switching is enabled, and
regulation of the ADP1972 control loop begins. As CSS continues
to charge and VSS rises, the PWM duty cycle gradually increases,
allowing the output voltage to rise linearly with little to no over-
shoot during startup. CSS charges and VSS rises until VSS reaches
the internal VREG voltage (5 V typical). When the internal system
duty cycle is less than the soft start duty cycle, the internal control
loop takes control of the ADP1972. See Figure 18 for a soft start
diagram.
There is an active, internal, pull-down resistor on the SS pin
that discharges CSS when the device shuts down to prevent a
fault from occurring.
VOUT
tREG
VREG
OPERATING MODES
The ADP1972 can be programmed to operate as an asynchronous
boost or as an asynchronous buck. If the MODE pin is driven
low by less than 1.05 V (typical), then the ADP1972 operates in
a boost configuration. A boost configuration is ideal for power
recycling and discharging in battery charging applications.
When the MODE pin is driven high by greater than 1.20 V
(typical), the ADP1972 operates in a buck configuration for
battery charging. See Figure 19 and Figure 20 for the ADP1972
behavior in each mode. When the ADP1972 is enabled, the
internal LDO regulator connected to the VREG pin also powers up.
On the rising edge of VREG, the state of the MODE pin is latched,
preventing the mode of operation from being changed while the
device is enabled. To change between boost and buck modes of
operation, shutdown or disable the ADP1972, adjust the MODE
pin to change the operating mode, and restart the system.
The operating mode can be changed when the EN pin is driven
low, the FAULT pin is driven low, or the ADP1972 is disabled
via a TSD event or UVLO condition. On the rising edge of the
FAULT control signal, the state of the MODE pin is latched,
preventing the mode of operation from being changed while the
device is enabled.
BOOST MODE CONFIGURATION
MODE ≤ 1.05V (TYPICAL)
VSCFG ≥ 4.53V (TYPICAL)
COMP
INTERNAL RAMP
(4V p-p)
4.5V
0.5V
0V
VREG (5V TYPICAL)
DH
0V
VREG (5V TYPICAL)
DL
0V
Figure 19. Signal Diagram for Boost Configuration
BUCK MODE CONFIGURATION
MODE ≥ 1.2V (TYPICAL)
VSCFG ≥ 4.53V (TYPICAL)
COMP
INTERNAL RAMP
(4V p-p)
DH
4.5V
0.5V
0V
VREG (5V TYPICAL)
0V
VREG (5V TYPICAL)
VSS
0.52V
0V
ENABLE
ADP1972
BEGIN
REGULATION
Figure 18. Soft Start Diagram
DL
0V
Figure 20. Signal Diagram for Buck Configuration
Rev. 0 | Page 11 of 20
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