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W49F002A Schematic ( PDF Datasheet ) - Winbond

Teilenummer W49F002A
Beschreibung 256K x 8 CMOS Flash Memory
Hersteller Winbond
Logo Winbond Logo 




Gesamt 22 Seiten
W49F002A Datasheet, Funktion
Preliminary W49F002A
256K × 8 CMOS FLASH MEMORY
GENERAL DESCRIPTION
The W49F002A is a 2-megabit, 5-volt only CMOS flash memory organized as 256K × 8 bits. The
device can be programmed and erased in-system with a standard 5V power supply. A 12-volt VPP is
not required. The unique cell architecture of the W49F002A results in fast program/erase operations
with extremely low current consumption (compared to other comparable 5-volt flash memory products).
The device can also be programmed and erased using standard EPROM programmers.
FEATURES
Single 5-volt operations:
5-volt Read
5-volt Erase
5-volt Program
Fast program operation:
Byte-by-byte programming: 35 µS (typ.)
Fast erase operation: 100 mS (typ.)
Fast read access time: 120 nS
Ten-year data retention
Hardware data protection
One 16K byte Boot Block with Lockout
protection
Typical page write (erase/program) cycles:
10 100
Two 8K byte parameter blocks
Two main memory blocks (96K, 128K) Bytes
Low power consumption
Active current: 25 mA (typ.)
Standby current: 20 µA (typ.)
Automatic program and erase timing with
internal VPP generation
End of program or erase detection
Toggle bit
Data polling
Latched address and data
TTL compatible I/O
JEDEC standard byte-wide pinouts
Available packages: 32-pin DIP and PLCC
Publication Release Date: September 12, 2001
- 1 - Revision A1
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W49F002A Datasheet, Funktion
Preliminary W49F002A
Any commands written to the chip during the Embedded Program Algorithm will be ignored. If a
hardware reset occurs during the programming operation, the data at that particular location will be
corrupted.
Programming is allowed in any sequence and across sector boundaries. Beware that a data "0" cannot
be programmed back to a "1". Only erase operations can convert "0"s to "1"s.
Refer to the Embedded Programming Algorithm using typical command strings and bus operations.
Chip Erase Command
Chip erase is a six-bus-cycle operation. There are two "unlock" write cycles. These are followed by
writing the "set-up" command. Two more "unlock" write cycles are then followed by the chip erase
command.
Chip erase does not require the user to program the device prior to erase. Upon executing the
Embedded Erase Algorithm command sequence the device will automatically erase and verify the
entire memory for an all one data pattern. The erase is performed sequentially on each sector at the
same time (see "Feature"). The system is not required to provide any controls or timings during these
operations.
The automatic erase begins on the rising edge of the last #WE pulse in the command sequence and
terminates when the data on DQ7 is "1" at which time the device returns to read the mode.
Refer to the Embedded Erase Algorithm using typical command strings and bus operations.
Sector Erase Command
Sector erase is a six bus cycle operation. There are two "unlock" write cycles. These are followed by
writing the "set-up" command. Two more "unlock" write cycles are then followed by the sector erase
command. The sector address (any address location within the desired sector) is latched on the falling
edge of #WE, while the command (30H) is latched on the rising edge of #WE.
Sector erase does not require the user to program the device prior to erase. When erasing a sector
or sectors the remaining unselected sectors are not affected. The system is not required to provide any
controls or timings during these operations.
The automatic sector erase begins after the rising edge of the #WE pulse for the last sector erase
command pulse and terminates when the data on DQ7, Data Polling, is "1."
Refer to the Embedded Erase Algorithm using typical command strings and bus operations.
Write Operation Status
DQ7: Data Polling
The W49F002A device features Data Polling as a method to indicate to the host that the embedded
algorithms are in progress or completed.
During the Embedded Program Algorithm, an attempt to read the device will produce the complement
of the data last written to DQ7. Upon completion of the Embedded Program Algorithm, an attempt to
read the device will produce the true data last written to DQ7.
During the Embedded Erase Algorithm, an attempt to read the device will produce a "0" at the DQ7
output. Upon completion of the Embedded Erase Algorithm, an attempt to read the device will produce
a "1" at the DQ7 output.
The flowchart for Data Polling (DQ7) is shown in "Data Polling Algorithm".
-6-
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W49F002A pdf, datenblatt
Preliminary W49F002A
DC CHARACTERISTICS
Absolute Maximum Ratings
PARAMETER
RATING
UNIT
Power Supply Voltage to VSS Potential
-0.5 to +7.0
V
Operating Temperature
0 to +70
°C
Storage Temperature
-65 to +150
°C
D.C. Voltage on Any Pin to Ground Potential except A9
-0.5 to VDD +1.0
V
Transient Voltage (<20 nS) on Any Pin to Ground Potential
-1.0 to VDD +1.0
V
Voltage on A9 Pin to Ground Potential
-0.5 to 12.5
V
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.
DC Operating Characteristics
(VDD = 5.0V ±10%, VSS = 0V, TA = 0 to 70° C)
PARAMETER SYM.
TEST CONDITIONS
Power Supply
Current
ICC #CE = #OE = VIL, #WE = VIH,
all DQs open
Address inputs = VIL/VIH, at f = 5 MHz
Standby VDD
Current (TTL input)
ISB1 #CE = VIH, all DQs open
Other inputs = VIL/VIH
Standby VDD Current ISB2 #CE = VDD -0.3V, all DQs open
(CMOS input)
Other inputs = VDD -0.3V/ VSS
Input Leakage
Current
ILI VIN = VSS to VDD
Output Leakage
Current
ILO VOUT = VSS to VDD
Input Low Voltage
VIL
-
Input High Voltage VIH
-
Output Low Voltage VOL IOL = 2.1 mA
Output High Voltage VOH IOH = -0.4 mA
LIMITS
MIN. TYP. MAX.
- 25
50
UNIT
mA
-2
3 mA
- 20 100
µA
- - 10 µA
- - 10 µA
-0.3 - 0.8 V
2.0 - VDD +0.5 V
--
0.45
V
2.4 - - V
- 12 -
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