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82801GB Schematic ( PDF Datasheet ) - Intel

Teilenummer 82801GB
Beschreibung I/O Controller Hub 7
Hersteller Intel
Logo Intel Logo 




Gesamt 70 Seiten
82801GB Datasheet, Funktion
Intel® I/O Controller Hub 7 (ICH7)
Family
Datasheet
— For the Intel® 82801GB ICH7, 82801GR ICH7R, 82801GDH ICH7DH,
82801GBM ICH7-M, 82801GHM ICH7-M DH, and 82801GU ICH7-U I/O
Controller Hubs
April 2007
Document Number: 307013-003
Free Datasheet http://www.datasheet4u.net/






82801GB Datasheet, Funktion
5.11
5.12
5.13
5.14
5.10.4.2 Level-Triggered Operation......................................................... 142
5.10.4.3 Registers Associated with Front Side Bus Interrupt Delivery .......... 142
5.10.4.4 Interrupt Message Format ........................................................ 142
Serial Interrupt (D31:F0) .................................................................................. 143
5.11.1 Start Frame ......................................................................................... 143
5.11.2 Data Frames ........................................................................................ 144
5.11.3 Stop Frame .......................................................................................... 144
5.11.4 Specific Interrupts Not Supported via SERIRQ........................................... 144
5.11.5 Data Frame Format ............................................................................... 145
Real Time Clock (D31:F0) ................................................................................. 146
5.12.1 Update Cycles ...................................................................................... 146
5.12.2 Interrupts ............................................................................................ 147
5.12.3 Lockable RAM Ranges............................................................................ 147
5.12.4 Century Rollover ................................................................................... 147
5.12.5 Clearing Battery-Backed RTC RAM ........................................................... 147
Processor Interface (D31:F0) ............................................................................ 149
5.13.1 Processor Interface Signals .................................................................... 149
5.13.1.1 A20M# (Mask A20).................................................................. 149
5.13.1.2 INIT# (Initialization)................................................................ 150
5.13.1.3 FERR#/IGNNE# (Numeric Coprocessor Error/ Ignore Numeric
Error) .................................................................................... 150
5.13.1.4 NMI (Non-Maskable Interrupt) .................................................. 151
5.13.1.5 Stop Clock Request and CPU Sleep (STPCLK# and CPUSLP#) ........ 151
5.13.1.6 CPU Power Good (CPUPWRGOOD) ............................................. 151
5.13.1.7 Deeper Sleep (DPSLP#) (Mobile/Ultra Mobile Only) ...................... 151
5.13.2 Dual-Processor Issues (Desktop Only) ..................................................... 152
5.13.2.1 Signal Differences ................................................................... 152
5.13.2.2 Power Management ................................................................. 152
Power Management (D31:F0) ............................................................................ 153
5.14.1 Features .............................................................................................. 153
5.14.2 Intel® ICH7 and System Power States ..................................................... 153
5.14.3 System Power Planes ............................................................................ 156
5.14.4 SMI#/SCI Generation ............................................................................ 156
5.14.4.1 PCI Express* SCI (Desktop and Mobile Only) .............................. 159
5.14.4.2 PCI Express* Hot-Plug (Desktop and Mobile Only) ....................... 159
5.14.5 Dynamic Processor Clock Control ............................................................ 159
5.14.5.1 Transition Rules among S0/Cx and Throttling States..................... 160
5.14.5.2 Deferred C3/C4 (Mobile/Ultra Mobile Only) ................................. 161
5.14.5.3 POPUP (Auto C3/C4 to C2) (Mobile/Ultra Mobile Only) .................. 161
5.14.5.4 POPDOWN (Auto C2 to C3/C4) (Mobile/Ultra Mobile Only) ............. 161
5.14.6 Dynamic PCI Clock Control (Mobile/Ultra Mobile Only)................................ 161
5.14.6.1 Conditions for Checking the PCI Clock ........................................ 162
5.14.6.2 Conditions for Maintaining the PCI Clock..................................... 162
5.14.6.3 Conditions for Stopping the PCI Clock ........................................ 162
5.14.6.4 Conditions for Re-Starting the PCI Clock ..................................... 162
5.14.6.5 LPC Devices and CLKRUN# (Mobile and Ultra Mobile Only) ............ 162
5.14.7 Sleep States ........................................................................................ 163
5.14.7.1 Sleep State Overview............................................................... 163
5.14.7.2 Initiating Sleep State ............................................................... 163
5.14.7.3 Exiting Sleep States................................................................. 163
5.14.7.4 PCI Express* WAKE# Signal and PME Event Message (
Desktop and Mobile only) ......................................................... 165
5.14.7.5 Sx-G3-Sx, Handling Power Failures ............................................ 165
5.14.8 Thermal Management............................................................................ 166
5.14.8.1 THRM# Signal......................................................................... 166
5.14.8.2 Processor Initiated Passive Cooling ............................................ 166
5.14.8.3 THRM# Override Software Bit ................................................... 167
6 Intel ® ICH7 Family Datasheet
Free Datasheet http://www.datasheet4u.net/

6 Page









82801GB pdf, datenblatt
8.2.4 PORT—PORT Interface Register (LAN Controller—B1:D8:F0) ....................... 319
8.2.5 EEPROM_CNTL—EEPROM Control Register (LAN Controller—B1:D8:F0)......... 321
8.2.6 MDI_CNTL—Management Data Interface (MDI) Control
Register (LAN Controller—B1:D8:F0) ....................................................... 322
8.2.7 REC_DMA_BC—Receive DMA Byte Count Register
(LAN Controller—B1:D8:F0) ................................................................... 322
8.2.8 EREC_INTR—Early Receive Interrupt Register
(LAN Controller—B1:D8:F0) ................................................................... 323
8.2.9 FLOW_CNTL—Flow Control Register (LAN Controller—B1:D8:F0) ................. 323
8.2.10 PMDR—Power Management Driver Register (LAN Controller—B1:D8:F0) ....... 324
8.2.11 GENCNTL—General Control Register (LAN Controller—B1:D8:F0)................. 325
8.2.12 GENSTA—General Status Register (LAN Controller—B1:D8:F0).................... 326
8.2.13 SMB_PCI—SMB via PCI Register (LAN Controller—B1:D8:F0) ...................... 326
8.2.14 Statistical Counters (LAN Controller—B1:D8:F0) ....................................... 327
8.3 ASF Configuration Registers (LAN Controller—B1:D8:F0) ....................................... 329
8.3.1 ASF_RID—ASF Revision Identification Register (LAN Controller—B1:D8:F0) .. 330
8.3.2 SMB_CNTL—SMBus Control Register (LAN Controller—B1:D8:F0) ................ 330
8.3.3 ASF_CNTL—ASF Control Register (LAN Controller—B1:D8:F0) ..................... 331
8.3.4 ASF_CNTL_EN—ASF Control Enable Register (ASF Controller—B1:D8:F0) ..... 332
8.3.5 ENABLE—Enable Register (ASF Controller—B1:D8:F0) ............................... 333
8.3.6 APM—APM Register (ASF Controller—B1:D8:F0) ........................................ 334
8.3.7 WTIM_CONF—Watchdog Timer Configuration Register
(ASF Controller—B1:D8:F0) ................................................................... 334
8.3.8 HEART_TIM—Heartbeat Timer Register (ASF Controller—B1:D8:F0)............. 335
8.3.9 RETRAN_INT—Retransmission Interval Register
(ASF Controller—B1:D8:F0) ................................................................... 335
8.3.10 RETRAN_PCL—Retransmission Packet Count Limit
Register (ASF Controller—B1:D8:F0) ....................................................... 336
8.3.11 ASF_WTIM1—ASF Watchdog Timer 1 Register
(ASF Controller—B1:D8:F0) ................................................................... 336
8.3.12 ASF_WTIM2—ASF Watchdog Timer 2 Register
(ASF Controller—B1:D8:F0) ................................................................... 336
8.3.13 PET_SEQ1—PET Sequence 1 Register (ASF Controller—B1:D8:F0) ............... 337
8.3.14 PET_SEQ2—PET Sequence 2 Register (ASF Controller—B1:D8:F0) ............... 337
8.3.15 STA—Status Register (ASF Controller—B1:D8:F0) ..................................... 338
8.3.16 FOR_ACT—Forced Actions Register (ASF Controller—B1:D8:F0)................... 339
8.3.17 RMCP_SNUM—RMCP Sequence Number Register
(ASF Controller—B1:D8:F0) ................................................................... 340
8.3.18 SP_MODE—Special Modes Register (ASF Controller—B1:D8:F0) .................. 340
8.3.19 INPOLL_TCONF—Inter-Poll Timer Configuration Register
(ASF Controller—B1:D8:F0) ................................................................... 340
8.3.20 PHIST_CLR—Poll History Clear Register (ASF Controller—B1:D8:F0) ............ 341
8.3.21 PMSK1—Polling Mask 1 Register (ASF Controller—B1:D8:F0) ...................... 341
8.3.22 PMSK2—Polling Mask 2 Register (ASF Controller—B1:D8:F0) ...................... 342
8.3.23 PMSK3—Polling Mask 3 Register (ASF Controller—B1:D8:F0) ...................... 342
8.3.24 PMSK4—Polling Mask 4 Register (ASF Controller—B1:D8:F0) ...................... 342
8.3.25 PMSK5—Polling Mask 5 Register (ASF Controller—B1:D8:F0) ...................... 343
8.3.26 PMSK6—Polling Mask 6 Register (ASF Controller—B1:D8:F0) ...................... 343
8.3.27 PMSK7—Polling Mask 7 Register (ASF Controller—B1:D8:F0) ...................... 343
8.3.28 PMSK8—Polling Mask 8 Register (ASF Controller—B1:D8:F0) ...................... 344
9 PCI-to-PCI Bridge Registers (D30:F0) .................................................................... 345
9.1 PCI Configuration Registers (D30:F0) ................................................................. 345
9.1.1 VID— Vendor Identification Register (PCI-PCI—D30:F0) ............................. 346
9.1.2 DID— Device Identification Register (PCI-PCI—D30:F0) ............................. 346
9.1.3 PCICMD—PCI Command (PCI-PCI—D30:F0) ............................................. 346
12 Intel ® ICH7 Family Datasheet
Free Datasheet http://www.datasheet4u.net/

12 Page





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