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PDF AND8276 Data sheet ( Hoja de datos )
| Número de pieza | AND8276 | |
| Descripción | Theory of Operation of V2 Controllers | |
| Fabricantes | ON Semiconductor | |
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AND8276/D
Theory of Operation of
V2 Controllers
with Emphasis on Applications using
MLCC’s for Output Filtering
Prepared by: Dennis Solley
ON Semiconductor
http://onsemi.com
APPLICATION NOTE
Every pulse width modulated controller configures basic
control elements such that when connected to the feedback
signal of a power converter, sufficient loop gain and
bandwidth is available to regulate the voltage set point
against line and load variations. These control elements
include error amplifier, pulse width modulator, ramp,
Switch Latch/Drive PWM
voltage reference, clock, latch and drive for the power
switch, which may or may not be integrated within the
controller. The arrangement of these elements differentiates
a voltage mode, or a current mode controller from a V2
device.
Figure 1 shows a basic voltage mode controller.
Error Amplifier
Z2
−
+
Z1
VREF
VFB
Clock
Voltage Ramp
Figure 1. V Mode Control
The converter’s feedback signal is compared against a
voltage reference and an error signal is generated at the
output of the voltage amplifier. This error signal is fed to one
input of a PWM, the other input being a voltage ramp of
fixed amplitude, generated from an internal clock. The
internal clock sets the latch to initiate a drive cycle. When the
error signal intersects the ramp, the PWM resets the latch
Switch Latch/Drive PWM
and the power switch is turned off. A small change in output
voltage, corresponding to input line or output load
variations, results in a change in the error voltage relative to
the ramp. This in turn causes the modulator’s duty cycle D
to change to regulate the output voltage.
Figure 2 highlights the elements of a current mode
controller.
Error Amplifier
Z2
−
+
Z1
VREF
VFB
Clock
© Semiconductor Components Industries, LLC, 2009
May, 2009 − Rev. 0
Current Ramp
Figure 2. I Mode Control
1
Publication Order Number:
AND8276/D
Free Datasheet http://www.datasheet4u.net/
1 page  
AND8276/D
Control Ramp Generation
In original V2 designs, the control ramp VCR was
generated from the converter’s output ripple. Using a
current derived ramp provides the same benefits as current
mode, namely input feedforward, single pole output filter
compensation and fast feedback following output load
transients. Typically a tantalum or organic polymer
capacitor was selected having a sufficiently large esr
component, relative to its capacitive and esl ripple
contributions, to ensure the control ramp was sensing
inductor current and its amplitude was sufficient to maintain
loop stability. This technique is illustrated in Figure 7. This
is a very simple technique but contrarian to the basic
requirement of a switching regulator to have low output
ripple. Component tolerances over time and temperature
also have to be considered.
VIN VOUT
L
Cesr
C
capacitor. Using this technique, output switching ripple
below 10 mV, can be readily obtained since parasitic esr and
esl ripple contributions are nil. In this case, the control ramp
is generated elsewhere in the circuit.
The control ramp used in V2 can be derived in a number
ways limited only by the designer’s individual creativity.
For example, one approach is to use the technique of
inductor DCR sensing to add a RC integrating network
across the output inductor and couple the “inductor sensed
current” ramp into the feedback path.
Another approach is to generate a voltage ramp from the
input switch node to add to the dc feedback signal. In this
way a voltage mode controller with inherent feed forward is
created.
Ramp Gerneration Using DCR Sensing
The technique is describes as referenced to the design of
a 12 V to 3.3 V buck converter running at 1 A load, using
MLCC capacitors for the output filter. The circuit of the
converter is given in Figure 8. The emphasis here is on the
control circuit and not on the loss terms in the power switch,
freewheel diode or inductor defining converter efficiency.
−
+
VREF
Figure 7. Control Ramp Generated from Output
Advances in multilayer ceramic capacitor technology are
such that MLCC’s can provide a cost effective filter solution
for low voltage (<12 V), high frequency converters
(>200 kHz) . For eg., a 10 mF MLCC 16 V in a 805 SMT
package has a esr of 2 mW and a esl of 100 nH. Using several
MLCC’s in parallel, connected to power and ground planes
on a PCB with multiple vias, can provide a “near perfect”
VIN
RC
VOUT
−
+ VREF
Figure 8. Control Ramp Generated from DCR
Inductor Sensing
http://onsemi.com
5
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