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AD9249 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD9249
Beschreibung 1.8 V ADC
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 36 Seiten
AD9249 Datasheet, Funktion
Data Sheet
FEATURES
Low power
16 ADC channels integrated into 1 package
58 mW per channel at 65 MSPS with scalable power options
35 mW per channel at 20 MSPS
SNR: 75 dBFS (to Nyquist); SFDR: 90 dBc (to Nyquist)
DNL: ±0.6 LSB (typical); INL: ±0.9 LSB (typical)
Crosstalk, worst adjacent channel, 10 MHz, −1 dBFS: −90 dB
typical
Serial LVDS (ANSI-644, default)
Low power, reduced signal option (similar to IEEE 1596.3)
Data and frame clock outputs
650 MHz full power analog bandwidth
2 V p-p input voltage range
1.8 V supply operation
Serial port control
Flexible bit orientation
Built in and custom digital test pattern generation
Programmable clock and data alignment
Power-down and standby modes
APPLICATIONS
Medical imaging
Communications receivers
Multichannel data acquisition
GENERAL DESCRIPTION
The AD9249 is a 16-channel, 14-bit, 65 MSPS analog-to-digital
converter (ADC) with an on-chip sample-and-hold circuit that
is designed for low cost, low power, small size, and ease of use.
The device operates at a conversion rate of up to 65 MSPS and
is optimized for outstanding dynamic performance and low power
in applications where a small package size is critical.
The ADC requires a single 1.8 V power supply and an LVPECL-/
CMOS-/LVDS-compatible sample rate clock for full performance
operation. No external reference or driver components are
required for many applications.
The AD9249 automatically multiplies the sample rate clock for the
appropriate LVDS serial data rate. Data clock outputs (DCO±1,
DCO±2) for capturing data on the output and frame clock outputs
(FCO±1, FCO±2) for signaling a new output byte are provided.
Individual channel power-down is supported, and the device
typically consumes less than 2 mW when all channels are disabled.
16 Channel, 14-Bit,
65 MSPS, Serial LVDS, 1.8 V ADC
AD9249
SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM
AVDD PDWN DRVDD
VIN+A1
VIN–A1
VIN+A2
VIN–A2
ADC
14
SERIAL
LVDS
AD9249
ADC
14
SERIAL
LVDS
D+A1
D–A1
D+A2
D–A2
VIN+H1
VIN–H1
VIN+H2
VIN–H2
ADC
14
SERIAL
LVDS
ADC
14
SERIAL
LVDS
VREF
SENSE
VCM1, VCM2
SYNC
REF
SELECT
1.0V
SERIAL PORT
INTERFACE
DATA
RATE
MULTIPLIER
RBIAS1,
RBIAS2
GND CSB1, SDIO/ SCLK/
CSB2 DFS DTP
Figure 1.
CLK+ CLK–
D+H1
D–H1
D+H2
D–H2
FCO+1, FCO+2
FCO–1, FCO–2
DCO+1, DCO+2
DCO–1, DCO–2
The ADC contains several features designed to maximize
flexibility and minimize system cost, such as programmable
clock and data alignment and programmable digital test pattern
generation.
The available digital test patterns include built-in deterministic
and pseudorandom patterns, along with custom user-defined test
patterns entered via the serial port interface (SPI).
The AD9249 is available in an RoHS-compliant, 144-ball CSP-
BGA. It is specified over the industrial temperature range of −40°C
to +85°C. This product is protected by a U.S. patent.
PRODUCT HIGHLIGHTS
1. Small Footprint. Sixteen ADCs are contained in a small,
10 mm × 10 mm package.
2. Low Power. 35 mW/channel at 20 MSPS with scalable power
options.
3. Ease of Use. Data clock outputs (DCO±1, DCO±2) operate
at frequencies of up to 455 MHz and support double data
rate (DDR) operation.
4. User Flexibility. SPI control offers a wide range of flexible
features to meet specific system requirements.
Rev. 0
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
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AD9249 Datasheet, Funktion
AD9249
Data Sheet
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted.
Table 3.
Parameter1
CLOCK INPUTS (CLK+, CLK−)
Logic Compliance
Differential Input Voltage2
Input Voltage Range
Input Common-Mode Voltage
Input Resistance (Differential)
Input Capacitance
LOGIC INPUTS (PDWN, SYNC, SCLK)
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
LOGIC INPUTS (CSB1, CSB2)
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
LOGIC INPUT (SDIO)
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
LOGIC OUTPUT (SDIO)3
Logic 1 Voltage (IOH = 800 μA)
Logic 0 Voltage (IOL = 50 μA)
DIGITAL OUTPUTS (D±x1, D±x2), ANSI-644
Logic Compliance
Differential Output Voltage (VOD)
Output Offset Voltage (VOS)
Output Coding (Default)
DIGITAL OUTPUTS (D±x1, D±x2), LOW POWER,
REDUCED SIGNAL OPTION
Logic Compliance
Differential Output Voltage (VOD)
Output Offset Voltage (VOS)
Output Coding (Default)
Temp Min
Full 0.2
Full GND − 0.2
Full
25°C
25°C
Full 1.2
Full 0
25°C
25°C
Full 1.2
Full 0
25°C
25°C
Full 1.2
Full 0
25°C
25°C
Full
Full
Full 281
Full 1.12
Full 150
Full 1.12
Typ Max
CMOS/LVDS/LVPECL
3.6
AVDD + 0.2
0.9
15
4
AVDD + 0.2
0.8
30
2
AVDD + 0.2
0.8
26
2
AVDD + 0.2
0.8
26
5
1.79
0.05
LVDS
350 422
1.22 1.38
Twos complement
LVDS
201 250
1.22 1.38
Twos complement
Unit
V p-p
V
V
pF
V
V
pF
V
V
pF
V
V
pF
V
V
mV
V
mV
V
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.
2 Specified for LVDS and LVPECL only.
3 Specified for 13 SDIO/DFS pins sharing the same connection.
Rev. 0 | Page 6 of 36
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AD9249 pdf, datenblatt
AD9249
Pin No.
M12, M11
M10, L10
M9, L9
M4, L4
M3, L3
M1, M2
L1, L2
K1, K2
J1, J2
H1, H2
G1, G2
M6, L6,
M7, L7
M5, L5,
M8, L8
F12
F11
E10, F10
G10
E12, E11
D12, D11
C12, C11
B12, B11
A12, A11
A10, B10
A9, B9
A8, B8
A7, B7
A6, B6
A5, B5
A4, B4
A3, B3
A1, A2
B1, B2
C1, C2
C8, C9
C7
C6
C4, C5
C3
Data Sheet
Mnemonic
D−C2, D+C2
D−D1, D+D1
D−D2, D+D2
D−E1, D+E1
D−E2, D+E2
D−F1, D+F1
D−F2, D+F2
D−G1, D+G1
D−G2, D+G2
D−H1, D+H1
D−H2, D+H2
DCO−1, DCO+1,
DCO−2, DCO+2
FCO−1, FCO+1,
FCO−2, FCO+2
SCLK/DTP
SDIO/DFS
CSB1, CSB2
PDWN
VIN−A1, VIN+A1
VIN−A2, VIN+A2
VIN−B1, VIN+B1
VIN−B2, VIN+B2
VIN−C1, VIN+C1
VIN−C2, VIN+C2
VIN−D1,
VIN+D1
VIN−D2,
VIN+D2
VIN−E1, VIN+E1
VIN−E2, VIN+E2
VIN−F1, VIN+F1
VIN−F2, VIN+F2
VIN−G1,
VIN+G1
VIN−G2,
VIN+G2
VIN−H1,
VIN+H1
VIN−H2,
VIN+H2
RBIAS1, RBIAS2
SENSE
VREF
VCM1, VCM2
SYNC
Description
Bank 2 Digital Output Complement, Bank 2 Digital Output True.
Bank 1 Digital Output Complement, Bank 1 Digital Output True.
Bank 2 Digital Output Complement, Bank 2 Digital Output True.
Bank 1 Digital Output Complement, Bank 1 Digital Output True.
Bank 2 Digital Output Complement, Bank 2 Digital Output True.
Bank 1 Digital Output Complement, Bank 1 Digital Output True.
Bank 2 Digital Output Complement, Bank 2 Digital Output True.
Bank 1 Digital Output Complement, Bank 1 Digital Output True.
Bank 2 Digital Output Complement, Bank 2 Digital Output True.
Bank 1 Digital Output Complement, Bank 1 Digital Output True.
Bank 2 Digital Output Complement, Bank 2 Digital Output True.
Data Clock Digital Output Complement, Data Clock Digital Output True. DCO±1 is used to
capture D±x1 digital output data; DCO±2 is used to capture D±x2 digital output data.
Frame Clock Digital Output Complement, Frame Clock Digital Output True. FCO±1 frames D±x1
digital output data; FCO±2 frames D±x2 digital output data.
Serial Clock (SCLK)/Digital Test Pattern (DTP).
Serial Data Input/Output (SDIO)/Data Format Select (DFS).
Chip Select Bar. CSB1 enables/disables SPI for eight channels in Bank 1; CSB2 enables/disables
SPI for eight channels in Bank 2.
Power-Down.
Analog Input Complement, Analog Input True.
Analog Input Complement, Analog Input True.
Analog Input Complement, Analog Input True.
Analog Input Complement, Analog Input True.
Analog Input Complement, Analog Input True.
Analog Input Complement, Analog Input True.
Analog Input Complement, Analog Input True.
Analog Input Complement, Analog Input True.
Analog Input Complement, Analog Input True.
Analog Input Complement, Analog Input True.
Analog Input Complement, Analog Input True.
Analog Input Complement, Analog Input True.
Analog Input Complement, Analog Input True.
Analog Input Complement, Analog Input True.
Analog Input Complement, Analog Input True.
Analog Input Complement, Analog Input True.
Sets analog current bias. Connect each RBIASx pin to a 10 kΩ (1% tolerance) resistor to ground.
Reference Mode Selection.
Voltage Reference Input/Output.
Analog Output Voltage at Midsupply. Sets the common mode of the analog inputs, external to
the ADC, as shown in Figure 35 and Figure 36.
Digital Input; Synchronizing Input to Clock Divider. This pin is internally pulled to ground by a
30 kΩ resistor.
Rev. 0 | Page 12 of 36
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