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83C251SP Schematic ( Datenblatt PDF ) - Intel

Teilenummer 83C251SP
Beschreibung HIGH-PERFORMANCE CHMOS MICROCONTROLLER
Hersteller Intel
Logo Intel Logo 

Gesamt 30 Seiten
		
83C251SP Datasheet, Funktion
PRELIMINARY
8XC251SA/SB/SP/SQ
HIGH-PERFORMANCE
CHMOS MICROCONTROLLER
Commercial/Express
s Real-time and Programmed Wait State
Bus Operation
s Binary-code Compatible with MCS® 51
s Pin Compatible with 44-pin PLCC and 40-
pin PDIP MCS 51 Sockets
s Register-based MCS® 251 Architecture
— 40-byte Register File
— Registers Accessible as Bytes, Words,
or Double Words
s Enriched MCS 51 Instruction Set
— 16-bit and 32-bit Arithmetic and Logic
Instructions
— Compare and Conditional Jump
Instructions
— Expanded Set of Move Instructions
s Linear Addressing
s 256-Kbyte Expanded External Code/Data
Memory Space
s ROM/OTPROM/EPROM Options:
16 Kbytes (SB/SQ), 8 Kbytes (SA/SP), or
without ROM/OTPROM/EPROM
s 16-bit Internal Code Fetch
s 64-Kbyte Extended Stack Space
s On-chip Data RAM Options:
1-Kbyte (SA/SB) or 512-Byte (SP/SQ)
s 8-bit, 2-clock External Code Fetch in
Page Mode
s Fast MCS 251 Instruction Pipeline
s User-selectable Configurations:
— External Wait States (0-3 wait states)
— Address Range & Memory Mapping
— Page Mode
s 32 Programmable I/O Lines
s Seven Maskable Interrupt Sources
with Four Programmable Priority
Levels
s Three Flexible 16-bit Timer/counters
s Hardware Watchdog Timer
s Programmable Counter Array
— High-speed Output
— Compare/Capture Operation
— Pulse Width Modulator
— Watchdog Timer
s Programmable Serial I/O Port
— Framing Error Detection
— Automatic Address Recognition
s High-performance CHMOS Technology
s Static Standby to 16-MHz Operation
s Complete System Development
Support
— Compatible with Existing Tools
— New MCS 251 Tools Available:
Compiler, Assembler, Debugger, ICE
s Package Options (PDIP, PLCC, and
Ceramic DIP)
A member of the Intel family of 8-bit MCS 251 microcontrollers, the 8XC251SA/SB/SP/SQ is binary-code
compatible with MCS 51 microcontrollers and pin compatible with 40-pin PDIP and 44-pin PLCC MCS 51
microcontrollers. MCS 251 microcontrollers feature an enriched instruction set, linear addressing, and
efficient C-language support. The 8XC251SA/SB/SP/SQ has 512 bytes or 1 Kbyte of on-chip RAM and is
available with 8 Kbytes or 16 Kbytes of on-chip ROM/OTPROM/EPROM, or without ROM/OTPROM/EPROM.
A variety of features can be selected by new user-programmable configurations.
COPYRIGHT © INTEL CORPORATION, 1996
May 1996
Order Number: 272783-003
Free Datasheet http://www.datasheet4u.com/






83C251SP Datasheet, Funktion
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
2.0 PINOUT
P1.5 / CEX2
P1.6 / CEX3 / WAIT#
P1.7 / CEX4 / A17 / WCLK
RST
P3.0 / RXD
VCC2
P3.1 / TXD
P3.2 / INT0#
P3.3 / INT1#
P3.4 / T0
P3.5 / T1
7 39
8
8XC251SA
38
9
10
8XC251SB
37
36
11 8XC251SP 35
12 8XC251SQ 34
13 33
14 32
15 View of component as 31
16 mounted on PC board 30
17 29
AD4 / P0.4
AD5 / P0.5
AD6 / P0.6
AD7 / P0.7
EA# /
VSS2
VPP
ALE / PROG#
PSEN#
A15 / P2.7
A14 / P2.6
A13 / P2.5
Figure 3. 8XC251SA/SB/SP/SQ 44-pin PLCC Package
A4205-02
6 PRELIMINARY
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83C251SP pdf, datenblatt
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
Table 6. Signal Descriptions (Continued)
Signal
Name
Type
Description
Alternate
Function
VPP I Programming Supply Voltage. The programming supply voltage is EA#
applied to this pin for programming the on-chip OTPROM/EPROM.
VSS
VSS1
GND
GND
Circuit Ground. Connect this pin to ground.
Secondary Ground. This ground is provided to reduce ground bounce
and improve power supply bypassing. Connection of this pin to ground
is recommended. However, when using the 8XC251SA/SB/SP/SQ as
a pin-for-pin replacement for the 8XC51BH, VSS1 can be unconnected
without loss of compatibility. (Not available on DIP)
VSS2
GND
Secondary Ground 2. This ground is provided to reduce ground
bounce and improve power supply bypassing. Connection of this pin to
ground is recommended. However, when using the 8XC251SB as a
pin-for-pin replacement for the 8XC51FX, VSS2 can be unconnected
without loss of compatibility. (Not available on DIP)
WAIT#
I Real-time Wait State Input. The real-time WAIT# input is enabled by P1.6/CEX3
writing a logical ‘1’ to the WCON.0 (RTWE) bit at S:A7H. During bus
cycles, the external memory system can signal ‘system ready’ to the
microcontroller in real time by controlling the WAIT# input signal on the
port 1.6 input.
WCLK
O Wait Clock Output. The real-time WCLK output is driven at port 1.7 P1.7/CEX4/
(WCLK) by writing a logical ‘1’ to the WCON.1 (RTWCE) bit at S:A7H. A17
When enabled, the WCLK output produces a square wave signal with
a period of one-half the oscillator frequency.
WR#
O Write. Write signal output to external memory.
P3.6
XTAL1
I Input to the On-chip, Inverting, Oscillator Amplifier. To use the
internal oscillator, a crystal/resonator circuit is connected to this pin. If
an external oscillator is used, its output is connected to this pin. XTAL1
is the clock source for internal timing.
XTAL2
O Output of the On-chip, Inverting, Oscillator Amplifier. To use the —
internal oscillator, a crystal/resonator circuit is connected to this pin. If
an external oscillator is used, leave XTAL2 unconnected.
The descriptions of A15:8/P2.7:0 and AD7:0/P0.7:0 are for the nonpage-mode chip configuration (com-
patible with 44-pin PLCC and 40-pin DIP MCS 51 microcontrollers). If the chip is configured for page-
mode operation, port 0 carries the lower address bits (A7:0), and port 2 carries the upper address bits
(A15:8) and the data (D7:0).
12
PRELIMINARY
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