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ACT8934A Schematic ( PDF Datasheet ) - Active-Semi

Teilenummer ACT8934A
Beschreibung Advanced PMU
Hersteller Active-Semi
Logo Active-Semi Logo 




Gesamt 30 Seiten
ACT8934A Datasheet, Funktion
ACT8934A
Rev 1, 22-Oct-12
Advanced PMU for Samsung S3C2416/S3C2450
FEATURES
Optimized for Samsung S3C2416/S3C2450
Processors
Three Step-Down DC/DC Converters
Four Low-Dropout Linear Regulators
Integrated ActivePathTM Charger
I2CTM Serial Interface
Advanced Enable/Disable Sequencing Controller
Minimal External Components
Tiny 5×5mm TQFN55-40 Package
0.75mm Package Height
Pb-Free and RoHS Compliant
GENERAL DESCRIPTION
The ACT8934A is a complete, cost effective, highly-
efficient ActivePMUTM power management solution,
optimized for the unique power, voltage-
sequencing, and control requirements of the
Samsung S3C2416/S3C2450 processors.
This device features three step-down DC/DC
converters and four low-noise, low-dropout linear
regulators, along with a complete battery charging
solution featuring the advanced ActivePathTM
system-power selection function.
The three DC/DC converters utilize a high-
efficiency, fixed-frequency (2MHz), current-mode
PWM control architecture that requires a minimum
number of external components. Two DC/DCs are
capable of supplying up to 900mA of output current,
while the third supports up to 700mA. All four low-
dropout linear regulators are high-performance,
low-noise regulators that supply up to 150mA,
150mA, 250mA, and 250mA, respectively.
The ACT8934A is available in a compact, Pb-Free
and RoHS-compliant TQFN55-40 package.
TYPICAL APPLICATION DIAGRAM
ACT8934A
Innovative PowerTM
ActivePMUTM and ActivePathTM are trademarks of Active-Semi.
I2CTM is a trademark of NXP.
-1-
www.active-semi.com
Copyright © 2012 Active-Semi, Inc.
Free Datasheet http://www.datasheet4u.com/






ACT8934A Datasheet, Funktion
ACT8934A
Rev 1, 22-Oct-12
PIN DESCRIPTIONS CONT’D
PIN NAME
DESCRIPTION
23
ISET
Charge Current Set. Program the charge current by connecting a resistor (RISET) between ISET
and GA. See the Charge Current Programming section for more information.
24
25
26
27
28
29, 30
31, 32
33
TH
VSEL
SCL
SDA
nSTAT
BAT
VSYS
CHGIN
Temperature Sensing Input. Connect to battery thermistor. TH is pulled up with a 102µA (typ) current
internally. See the Battery Temperature Monitoring section for more information.
Step-Down DC/DCs Output Voltage Selection. Drive to logic low to select default output voltage.
Drive to logic high to select secondary output voltage. See the Output Voltage Programming
section for more information.
Clock Input for I2C Serial Interface.
Data Input for I2C Serial Interface. Data is read on the rising edge of SCL.
Active-Low Open-Drain Charger Status Output. nSTAT has a 8mA (typ) current limit, allowing it
to directly drive an indicator LED without additional external components. See the Charge Status
Indicator section for more information.
Battery Charger Output. Connect this pin directly to the battery anode (+ terminal)
System Output Pin. Bypass to GA with a 10µF or larger ceramic capacitor.
Power Input for the Battery Charger. Bypass CHGIN to GA with a capacitor placed as close to
the IC as possible. The battery charger is automatically enabled when a valid voltage is present
on CHGIN.
34 OUT2 Output Feedback Sense for REG2.
35
VP2
Power Input for REG2. Bypass to GP12 with a high quality ceramic capacitor placed as close to
the IC as possible.
36 SW2 Switching Node Output for REG2.
37
GP12
Power Ground for REG1 and REG2. Connect GA, GP12 and GP3 together at a single point as
close to the IC as possible.
38 SW1 Switching Node Output for REG1.
39
VP1
Power Input for REG1. Bypass to GP12 with a high quality ceramic capacitor placed as close to
the IC as possible.
40 NC No Connect. Not internally connected.
EP EP Exposed Pad. Must be soldered to ground on PCB.
Innovative PowerTM
ActivePMUTM and ActivePathTM are trademarks of Active-Semi.
I2CTM is a trademark of NXP.
-6-
www.active-semi.com
Copyright © 2012 Active-Semi, Inc.
Free Datasheet http://www.datasheet4u.com/

6 Page









ACT8934A pdf, datenblatt
ACT8934A
Rev 1, 22-Oct-12
REGISTER AND BIT DESCRIPTIONS CONT’D
OUTPUT ADDRESS BIT
REG4
0x51
[0]
REG5
0x54 [7:6]
REG5
0x54 [5:0]
REG5
0x55
[7]
REG5
0x55
[6]
REG5
REG5
REG5
REG5
REG6
REG6
REG6
0x55
0x55
0x55
0x55
0x60
0x60
0x61
[5]
[4:2]
[1]
[0]
[7:6]
[5:0]
[7]
REG6
0x61
[6]
REG6
REG6
REG6
REG6
REG7
REG7
REG7
0x61
0x61
0x61
0x61
0x64
0x64
0x65
[5]
[4:2]
[1]
[0]
[7:6]
[5:0]
[7]
REG7
0x65
[6]
REG7
REG7
REG7
REG7
0x65
0x65
0x65
0x65
[5]
[4:2]
[1]
[0]
NAME
OK
-
VSET
ON
DIS
LOWIQ
DELAY
nFLTMSK
OK
-
VSET
ON
DIS
LOWIQ
DELAY
nFLTMSK
OK
-
VSET
ON
DIS
LOWIQ
DELAY
nFLTMSK
OK
ACCESS
DESCRIPTION
R
Regulator Power-OK Status. Value is 1 when output voltage
exceeds the power-OK threshold, value is 0 otherwise.
R Reserved.
R/W
Output Voltage Selection. See the Output Voltage
Programming section for more information.
R/W
Regulator Enable Bit. Set bit to 1 to enable the regulator,
clear bit to 0 to disable the regulator.
Output Discharge Control. When activated, LDO output is
R/W
discharged to GA through 1.5kresistor when in shutdown.
Set bit to 1 to enable output voltage discharge in shutdown,
clear bit to 0 to disable this function.
R/W
LDO Low-IQ Mode Control. Set bit to 1 for low-power
operating mode, clear bit to 0 for normal mode.
R/W
Regulator Turn-On Delay Control. See the REG4, REG5,
REG6, REG7 Turn-on Delay section for more information.
R/W
Regulator Fault Mask Control. Set bit to 1 enable fault-
interrupts, clear bit to 0 to disable fault-interrupts.
R
Regulator Power-OK Status. Value is 1 when output voltage
exceeds the power-OK threshold, value is 0 otherwise.
R Reserved.
R/W
Output Voltage Selection. See the Output Voltage
Programming section for more information.
R/W
Regulator Enable Bit. Set bit to 1 to enable the regulator,
clear bit to 0 to disable the regulator.
Output Discharge Control. When activated, LDO output is
R/W
discharged to GA through 1.5kresistor when in shutdown.
Set bit to 1 to enable output voltage discharge in shutdown,
clear bit to 0 to disable this function.
R/W
LDO Low-IQ Mode Control. Set bit to 1 for low-power
operating mode, clear bit to 0 for normal mode.
R/W
Regulator Turn-On Delay Control. See the REG4, REG5,
REG6, REG7 Turn-on Delay section for more information.
R/W
Regulator Fault Mask Control. Set bit to 1 enable fault-
interrupts, clear bit to 0 to disable fault-interrupts.
R
Regulator Power-OK Status. Value is 1 when output voltage
exceeds the power-OK threshold, value is 0 otherwise.
R Reserved.
R/W
Output Voltage Selection. See the Output Voltage
Programming section for more information.
R/W
Regulator Enable Bit. Set bit to 1 to enable the regulator,
clear bit to 0 to disable the regulator.
Output Discharge Control. When activated, LDO output is
R/W
discharged to GA through 1.5kresistor when in shutdown.
Set bit to 1 to enable output voltage discharge in shutdown,
clear bit to 0 to disable this function.
R/W
LDO Low-IQ Mode Control. Set bit to 1 for low-power
operating mode, clear bit to 0 for normal mode.
R/W
Regulator Turn-On Delay Control. See the REG4, REG5,
REG6, REG7 Turn-on Delay section for more information.
R/W
Regulator Fault Mask Control. Set bit to 1 enable fault-
interrupts, clear bit to 0 to disable fault-interrupts.
R
Regulator Power-OK Status. Value is 1 when output voltage
exceeds the power-OK threshold, value is 0 otherwise.
Innovative PowerTM
ActivePMUTM and ActivePathTM are trademarks of Active-Semi.
I2CTM is a trademark of NXP.
- 12 -
www.active-semi.com
Copyright © 2012 Active-Semi, Inc.
Free Datasheet http://www.datasheet4u.com/

12 Page





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