|
|
PDF APL3218 Data sheet ( Hoja de datos )
| Número de pieza | APL3218 | |
| Descripción | Li+ Charger Protection IC | |
| Fabricantes | ANPEC | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de APL3218 (archivo pdf) en la parte inferior de esta página. Total 20 Páginas | ||
|
No Preview Available !
APL3218
Li+ Charger Protection IC
Features
General Description
• Provide OUT Pin 5V Voltage Clamping Protection
• Thermal Charging Regulation Protection
• Provide Input Over-voltage Protection
• Provide Input Over-current Protection
• Provide Over Temperature Protection
• Provide Reverse Current Blocking
• High Immunity of False Triggering
• High Accuracy Protection Threshold
• Low On Resistance 0.75Ω Typ.
• Compact TDFN2x2-8 and DFN3x3-8 Packages
• Lead Free and Green Devices Available
(RoHS Compliant)
Applications
• Cell Phones
Pin Configuration
The APL3218 provides complete Li+ charger protection
against Input over-voltage, input over-current and over-
temperature. When any of the monitored parameters is
over the threshold, the IC turns off the charging current.
All protections also have deglitch time against false trig-
gering due to voltage spikes or current transients.
The APL3218 integrates a 5.5V LDO to prevent ACIN over-
shoot reaching CHR_LDO and OUT. When any transient
peak voltage above 5.5V presenting in ACIN pin, but be-
low OVP threshold, the internal LDO will clamp its output
at 5.5V. When ACIN voltage exceeds OVP threshold, the
device will turn off charging current. The charging current
is controlled by the GATDRV pin. When sourcing a cur-
rent from the GATDRV pin, the OUT pin delivers the charg-
ing current which is 200-fold magnified in amplitude
based on GATDRV’s current.
Other features include accurate V /V Voltage divider,
VCDT ACIN
reverse current blocking from OUT to ACIN and OTP
protection. The APL3218 provides complete Li+ charger
protections, and saves the external MOSFET and Schottky
diode for the charger of cell phone’s PMIC. The above
features and small package make the APL3218 an ideal
part for cell phones applications.
ACIN 1
ACIN 2
GND 3
VCDT 4
8 OUT
7 OUT
6 CHR_LDO
5 GATDRV
DFN3x3-8
(Top View)
ACIN 1
ACIN 2
GND 3
VCDT 4
8 OUT
7 OUT
6 CHR_LDO
5 GATDRV
TDFN2x2-8
(Top View)
= Exposed Pad (connected to ground
plane for better heat dissipation)
Simplified Application Circuit
5V
Adapter
ACIN CHR_LDO
APL3218
GATDRV
VCDT
OUT
GND
Li+
Battery
CHR_LDO
PMIC
GATDRV
VCDT
ISENS
VBAT
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Copyright © ANPEC Electronics Corp.
Rev. A.1 - Apr., 2012
1
www.anpec.com.tw
Free Datasheet http://www.datasheet4u.com/
1 page  
APL3218
Typical Operating Characteristics
ACIN Supply Current vs. ACIN Input
Voltage
600
TJ=25
500
400
300
200
100
0
012 34 56 78 9
ACIN Input Voltage (V)
Over Current Trip Threshold vs.
Junction Temperature
2.0
1.8 VACIN =5V
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
-50 -25 0 25 50 75 100 125
Junction Temperature (oC)
ACIN POR Threshold vs. Junction
Temperature
2.8
2.7
VACIN Rising
2.6
2.5
2.4
2.3 VACIN Falling
2.2
2.1
2.0
-50 -25
0
25 50 75 100 125
Junction Temperature (oC)
Copyright © ANPEC Electronics Corp.
Rev. A.1 - Apr., 2012
5
ACIN Supply Current vs. Junction
Temperature
600
VACIN =5V
550
500
450
400
350
300
250
200
-50 -25 0 25 50 75 100
Junction Temperature (oC
Current Limit Level vs. Junction
Temperature
1.6
1.4 VACIN =5V
125
1.2
1.0
0.8
0.6
0.4
0.2
0.0
-50 -25 0 25 50 75 100 125
Junction Temperature (oC)
Input OVP Threshold vs. Junction
10.5 Temperature
10.4
10.3
10.2
10.1
10.0
VACIN Rising
9.9
9.8
9.7
9.6
9.5
-50
VACIN Falling
-25 0 25 50 75 100 125
Junction Temperature (oC)
www.anpec.com.tw
Free Datasheet http://www.datasheet4u.com/
5 Page 
APL3218
Function Description
ACIN Power-On-Reset (POR)
The APL3218 is built-in a power-on-reset circuit to keep
the output shut off until internal circuitry is operating
properly. The POR circuit has hysteresis and a de-glitch
feature so that it will typically ignore undershoot transients
on the input. When input voltage exceeds the POR thresh-
old and after 8ms blanking time, the output voltage starts
a soft-start to reduce the inrush current.
ACIN Over-Voltage Protection (OVP) and LDO Mode
Operation
The CHR_LDO output of the IC operates similar to a lin-
ear regulator. When the ACIN input voltage is less than
V , and above the ACIN POR V , the internal LDO
REG
ACIN
output voltage tracks the input voltage with a voltage drop
caused by RDS(on) of MOSFET Q1. When the ACIN input
voltage is greater than VREG plus the RDS(on) drop of Q1,
and less than VOVP, the internal LDO output voltage is
regulated to V , and this is also referred as LDO mode
REG
operation. If the input voltage rises above V , the inter-
OVP
nal FET Q1 and Q2 will be turned off within 1µs to protect
connected system on OUT pin. When the input voltage
returns below the input OVP threshold minus the
hysteresis, the FETs is turned on again after 1ms recov-
ery time. The input OVP circuit has a 200mV hysteresis
and a recovery time of T
to provide noise immunity
ON(OVP)
against transient conditions.
Charging Current Control
The charging current is controlled by the GATDRV pin.
When sourcing a current from the GATDRV pin, the OUT
pin delivers the charging current which is 200-fold mag-
nified in amplitude based on GATDRV’s current. The IOUT
current can be calculated by this following equation:
Current Limit
The output current is monitored by the internal current
limit circuit. When the output current reaches the current
limit threshold, the device limits the output current at cur-
rent limit threshold. The current limit level decrease as
the junction temperature increase. When the Junction
temperature increases, the internal current limit circuit
reduces the current limit level, allowing the device’s Junc-
tion temperature to cool down. (See Figure 1)
Internal P-MOSFET and Reverse Current Blocking
The APL3218 integrates a P-channel MOSFET with the
body diode reverse protection to replace the external PNP
transistor and Schottky diode for cell phone?¦s PMIC. The
body diode reverse protection prevents battery voltage
supplies to CHR_LDO and ACIN pin. When the P-chan-
nel MOSFET’s negative VSD voltage is detected, the inter-
nal bulk selection circuitry will switch the body diode of
the P-channel MOSFET forward biased from source to
drain, meanwhile the P-channel is turned off regardless
of GATDRV’s current. This after the detection of negative
VSD, the P-channel MOSFET is in lockout state to prevent
battery discharging from ACIN and CHR_LDO to external
circuitry. The P-channel MOSFET lockout will be releases
when positive VSD is detected.
OUT Overshoot Clamp
This OUT pin possesses the overshoot clamp function to
limit peak voltage. Since the clamping function needs a
low resistance path between OUT pin and external high
voltage source (in abnormal condition), please connect
this OUT pin directly to outside circuit to let clamping work.
I =200xI
OUT
GATDRV
where
The IOUT is the current flowing out from OUT pin.
The IGATDRV is the current flowing out from GATDRV pin.
Copyright © ANPEC Electronics Corp.
Rev. A.1 - Apr., 2012
11
www.anpec.com.tw
Free Datasheet http://www.datasheet4u.com/
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet APL3218.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| APL3212A | (APL3212A/B/C) Li+ Charger Protection IC | ANPEC |
| APL3212B | (APL3212A/B/C) Li+ Charger Protection IC | ANPEC |
| APL3212C | (APL3212A/B/C) Li+ Charger Protection IC | ANPEC |
| APL3213 | Li+ Charger Protection IC | ANPEC |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |