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PDF AD9887A Data sheet ( Hoja de datos )
| Número de pieza | AD9887A | |
| Descripción | Dual Interface | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
Analog interface
170 MSPS maximum conversion rate
Programmable analog bandwidth
0.5 V to 1.0 V analog input range
500 ps p-p PLL clock jitter at 170 MSPS
3.3 V power supply
Full sync processing
Midscale clamping
4:2:2 output format mode
Digital interface
DVI 1.0-compatible interface
170 MHz operation (2 pixels/clock mode)
High skew tolerance of 1 full input clock
Sync detect for hot plugging
Supports high bandwidth digital content protection
APPLICATIONS
RGB graphics processing
LCD monitors and projectors
Plasma display panels
Scan converters
Microdisplays
Digital TVs
GENERAL DESCRIPTION
The AD9887A offers an analog interface receiver and a digital
visual interface (DVI) receiver integrated on a single chip,
supports high bandwidth digital content protection (HDCP),
and is software and pin-to-pin compatible with the AD9887.
Analog Interface
The complete 8-bit, 170 MSPS, monolithic analog interface is
optimized for capturing RGB graphics signals from personal
computers and workstations. Its 170 MSPS encode rate capability
and full-power analog bandwidth of 330 MHz support resolutions
of up to 1600 × 1200 (UXGA) at 60 Hz. The interface includes
a 170 MHz triple ADC with internal 1.25 V reference; a phase-
locked loop (PLL); and programmable gain, offset, and clamp
controls. The user provides only a 3.3 V power supply, analog
input, and Hsync. Three-state CMOS outputs can be powered
from 2.5 V to 3.3 V. The analog interface also offers full sync
processing for composite sync and sync-on-green (SOG) appli-
cations. The AD9887A on-chip PLL generates a pixel clock from
Hsync with output frequencies ranging from 12 MHz to 170 MHz.
PLL clock jitter is typically 500 ps p-p at 170 MSPS.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
Dual Interface for
Flat Panel Display
AD9887A
FUNCTIONAL BLOCK DIAGRAM
REFIN
RAIN
GAIN
BAIN
HSYNC
VSYNC
COAST
CLAMP
CKINV
CKEXT
FILT
SOGIN
SCL
SDA
A1
A0
Rx0+
Rx0–
Rx1+
Rx1–
Rx2+
Rx2–
RxC+
RxC–
RTERM
DDCSCL
DDCSDA
MCL
MDA
ANALOG INTERFACE
CLAMP
CLAMP
CLAMP
A/D
A/D
A/D
SYNC
PROCESSING
AND CLOCK
GENERATION
REF
8 8 ROUTA
8 ROUTB
8
8 GOUTA
8 GOUTB
8 8 BOUTA
8
2 DATACK
HSOUT
VSOUT
SOGOUT
SCDT
SERIAL REGISTER
AND
POWER MANAGEMENT
DIGITAL INTERFACE
8
8
DVI
RECEIVER
8
2
8 ROUTA
8 ROUTB
8 GOUTA
8 GOUTB
8 BOUTA
8 BOUTB
DATACK
DE
HSOUT
VSOUT
REFOUT
8 RED A
8 RED B
8 GREEN A
8 GREEN B
8 BLUE A
8 BLUE B
2 DATACK
HSOUT
VSOUT
SOGOUT
DE
HDCP
AD9887A
Figure 1.
Digital Interface
The AD9887A contains a DVI 1.0-compatible receiver and
supports resolutions up to 1600 × 1200 (UXGA) at 60 Hz. The
receiver operates with true color (24-bit) panels in one or two
pixel(s) per clock mode and features an intrapair skew tolerance
of up to one full clock cycle. With the inclusion of HDCP,
displays can receive encrypted video content. The AD9887A
allows for authentication of a video receiver, decryption of encoded
data at the receiver, and renewability of authentication during
transmission, as specified by the HDCP v1.0 protocol. Fabricated
in an advanced CMOS process, the AD9887A is provided in a
160-lead, surface-mount, plastic MQFP and is specified over the
0°C to 70°C temperature range. The AD9887A is also available
in an RoHS compliant package.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2003–2007 Analog Devices, Inc. All rights reserved.
Free Datasheet http://www.datasheet4u.com/
1 page  
AD9887A
DIGITAL INTERFACE
VD = 3.3 V, VDD = 3.3 V, clock = maximum, unless otherwise noted.
Table 2.
Parameter
RESOLUTION
DC DIGITAL I/O SPECIFICATIONS
High Level Input Voltage, VIH
Low Level Input Voltage, VIL
High Level Output Voltage, VOH
Low Level Output Voltage, VOL
Input Clamp Voltage, VCINL
Input Clamp Voltage, VCIPL
Output Clamp Voltage, VCONL
Output Clamp Voltage, VCOPL
Output Leakage Current, IOL
DC SPECIFICATIONS
Output High Drive, IOHD (VOUT = VOH)
Conditions
ICL = −18 mA
ICL = +18 mA
ICL = −18 mA
ICL = +18 mA
High impedance
Output drive = high
Output drive = med
Output drive = low
Test
Temp Level
Full VI
Full VI
Full VI
Full VI
IV
IV
IV
IV
Full IV
Full IV
Full IV
Full IV
Output Low Drive, IOLD (VOUT = VOL)
Output drive = high
Output drive = med
Output drive = low
Full IV
Full IV
Full IV
DATACK High Drive, IOHC (VOUT = VOH)
Output drive = high
Output drive = med
Output drive = low
Full IV
Full IV
Full IV
DATACK Low Drive, IOLC (VOUT = VOL)
Differential Input Voltage,
Single-Ended Amplitude
POWER SUPPLIES
VD Supply Voltage
VDD Supply Voltage
PVD Supply Voltage
ID Supply Current1
IDD Supply Current1, 2
IPVD Supply Current1
Total Supply Current with HDCP1, 2
AC SPECIFICATIONS
Intrapair (+ to −) Differential Input Skew, TDPS
Channel-to-Channel Differential Input Skew,
TCCS
Low-to-High Transition Time for Data and
Controls, DLHT
Output drive = high
Output drive = med
Output drive = low
Full IV
Full IV
Full IV
Full IV
Minimum value for two pixels
per clock mode
Full IV
Full IV
Full
25°C
255°C
255°C
IV
V
V
IV
VI
Full
Full
Output drive = high; CL = 10 pF Full
Output drive = med; CL = 7 pF Full
Output drive = low; CL = 5 pF Full
IV
IV
IV
IV
IV
AD9887AKS
Min Typ Max
8
Unit
Bits
2.6 V
0.8
2.4 V
0.4 V
GND − 0.8 V
VDD + 0.8 V
GND − 0.8 V
VDD + 0.8 V
−10 +10 μA
13 mA
8 mA
5 mA
−9 mA
−7 mA
−5 mA
25 mA
12 mA
8 mA
−25
−19
−8
75 800
mA
mA
mA
mA
3.15 3.3
2.2 3.3
3.45
3.45
3.15 3.3
350
40
130
520
3.45
560
360
1.0
2.5
3.1
5.4
V
V
V
mA
mA
mA
mA
ps
Clock
period
ns
ns
ns
Rev. B | Page 5 of 52
Free Datasheet http://www.datasheet4u.com/
5 Page 
AD9887A
PIN FUNCTION DETAILS—PINS SHARED BETWEEN DIGITAL AND ANALOG INTERFACES
Sync Outputs
Data Clock Outputs
HSOUT Horizontal Sync Output
DATACK Data Output Clock
VSOUT
The horizontal sync output is a reconstructed
version of the video Hsync, phase-aligned with
DATACK. The polarity of this output can be
controlled via a serial bus bit. In analog interface
mode, the placement and duration are variable. In
digital interface mode, the placement and duration
are set by the graphics transmitter.
Vertical Sync Output
DATACK Data Output Clock Complement
Like the data outputs, the data clock outputs are
shared between the two interfaces. They also behave
differently, depending on which interface is active.
See the Theory of Operation and Design Guide—
Analog Interface and the Theory of Operation—
Digital Interface sections for details on how these
pins behave.
The Vsync is separated from a composite signal or
a direct pass-through of the Vsync input. The polarity
of this output can be controlled via a serial bus bit.
The placement and duration in all modes are set by
the graphics transmitter.
2-Wire Serial Port
SDA Serial Port Data I/O
SCL Serial Port Data Clock
A0 Serial Port Address Input 1
Sync Detect
SCDT Chip Active/Inactive Detect Output
The logic for the SCDT pin is analog interface
HSYNC detection or digital interface DE detection.
Therefore, the SCDT pin switches to logic low under
two conditions: when neither interface is active, or
when the chip is in full power-down mode. The data
outputs are automatically set to three-state when
SCDT is low. This pin can be read by a controller to
identify periods of inactivity.
A1 Serial Port Address Input 2
Scan Function
For a full description of the 2-wire serial register
and how it works, see the 2-Wire Serial Control
Port section.
Data Outputs
RED A Data Output, Red Channel, Port A/Even
RED B Data Output, Red Channel, Port B/Odd
GREEN A Data Output, Green Channel, Port A/Even
GREEN B Data Output, Green Channel, Port B/Odd
BLUE A Data Output, Blue Channel, Port A/Even
BLUE B Data Output, Blue Channel, Port B/Odd
SCANIN Data Input for Scan Function
By using the scan function, 48 bits of data can be
loaded into the data outputs. Data is input serially
through this pin, clocked with the SCANCLK pin,
and comes through the outputs as parallel words.
This function is useful for loading known data into
a graphics controller chip for testing purposes.
SCANOUT Data Output for Scan Function
The data input serially into the SCANIN register can
be read through this pin. Data is read on a FIFO
basis and is clocked via the SCANCLK pin.
These outputs are the main data outputs. Bit 7 is the
MSB. These outputs are shared between the two
interfaces.
SCANCLK
Data Clock for Scan Function
This pin clocks the data for the scan function.
It controls both data input and output.
Rev. B | Page 11 of 52
Free Datasheet http://www.datasheet4u.com/
11 Page | ||
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