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AD5142 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD5142
Beschreibung (AD5122 / AD5142) Nonvolatile Digital Potentiometer
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
AD5142 Datasheet, Funktion
Data Sheet
Dual Channel, 128-/256-Position, SPI,
Nonvolatile Digital Potentiometer
AD5122/AD5142
FEATURES
10 kΩ and 100 kΩ resistance options
Resistor tolerance: 8% maximum
Wiper current: ±6 mA
Low temperature coefficient: 35 ppm/°C
Wide bandwidth: 3 MHz
Fast start-up time < 75 µs
Linear gain setting mode
Single- and dual-supply operation
Independent logic supply: 1.8 V to 5.5 V
Wide operating temperature: −40°C to +125°C
3 mm × 3 mm package option
4 kV ESD protection
APPLICATIONS
Portable electronics level adjustment
LCD panel brightness and contrast controls
Programmable filters, delays, and time constants
Programmable power supplies
GENERAL DESCRIPTION
The AD5122/AD5142 potentiometers provides a nonvolatile
solution for 128-/256-position adjustment applications, offering
guaranteed low resistor tolerance errors of ±8% and up to ±6 mA
current density in the Ax, Bx, and Wx pins.
The low resistor tolerance and low nominal temperature coefficient
simplify open-loop applications as well as applications requiring
tolerance matching.
The linear gain setting mode allows independent programming
of the resistance between the digital potentiometer terminals,
through the RAW and RWB string resistors, allowing very accurate
resistor matching.
The high bandwidth and low total harmonic distortion (THD)
ensure optimal performance for ac signals, making these
devices suitable for filter design.
The low wiper resistance of only 40 Ω at the ends of the resistor
array allows for pin-to-pin connection.
The wiper values can be set through an SPI-compatible digital
interface that is also used to read back the wiper register and
EEPROM contents.
The AD5122/AD5142 is available in a compact, 16-lead, 3 mm ×
3 mm LFCSP and a 16-lead TSSOP. The parts are guaranteed to
operate over the extended industrial temperature range of −40°C
to +125°C.
FUNCTIONAL BLOCK DIAGRAM
VLOGIC
VDD
INDEP
POWER-ON
RESET
AD5122/
AD5142
RESET
SCLK
SDI
SYNC
SDO
SERIAL
INTERFACE 7/8
RDAC1
INPUT
REGISTER 1
RDAC2
INPUT
REGISTER 2
EEPROM
MEMORY
A1
W1
B1
A2
W2
B2
GND VSS
Figure 1.
Table 1. Family Models
Model
Channel Position
AD51231 Quad
128
AD5124 Quad
128
AD5124 Quad
128
AD51431 Quad
256
AD5144 Quad
256
AD5144 Quad
256
AD5144A Quad
256
AD5122 Dual
128
AD5122A Dual
128
AD5142 Dual
256
AD5142A Dual
256
AD5121 Single
128
AD5141 Single
256
Interface
I2C
SPI/I2C
SPI
I2C
SPI/I2C
SPI
I2C
SPI
I2C
SPI
I2C
SPI/I2C
SPI/I2C
Package
LFCSP
LFCSP
TSSOP
LFCSP
LFCSP
TSSOP
TSSOP
LFCSP/TSSOP
LFCSP/TSSOP
LFCSP/TSSOP
LFCSP/TSSOP
LFCSP
LFCSP
1 Two potentiometers and two rheostats.
Rev. 0
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2012 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
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AD5142 Datasheet, Funktion
AD5122/AD5142
Data Sheet
ELECTRICAL CHARACTERISTICS—AD5142
VDD = 2.3 V to 5.5 V, VSS = 0 V; VDD = 2.25 V to 2.75 V, VSS = −2.25 V to −2.75 V; VLOGIC = 1.8 V to 5.5 V, −40°C < TA < +125°C, unless
otherwise noted.
Table 3.
Parameter
DC CHARACTERISTICS—RHEOSTAT
MODE (ALL RDACs)
Resolution
Resistor Integral Nonlinearity2
Resistor Differential Nonlinearity2
Nominal Resistor Tolerance
Resistance Temperature Coefficient3
Wiper Resistance3
Bottom Scale or Top Scale
Nominal Resistance Match
DC CHARACTERISTICS—POTENTIOMETER
DIVIDER MODE (ALL RDACs)
Integral Nonlinearity4
Differential Nonlinearity4
Full-Scale Error
Zero-Scale Error
Voltage Divider Temperature
Coefficient3
Symbol
Test Conditions/Comments
N
R-INL
R-DNL
ΔRAB/RAB
(ΔRAB/RAB)/ΔT × 106
RW
RBS or RTS
RAB1/RAB2
RAB = 10 kΩ
VDD ≥ 2.7 V
VDD < 2.7 V
RAB = 100 kΩ
VDD ≥ 2.7 V
VDD < 2.7 V
Code = full scale
Code = zero scale
RAB = 10 kΩ
RAB = 100 kΩ
RAB = 10 kΩ
RAB = 100 kΩ
Code = 0xFF
INL
DNL
VWFSE
VWZSE
(ΔVW/VW)/ΔT × 106
RAB = 10 kΩ
RAB = 100 kΩ
RAB = 10 kΩ
RAB = 100 kΩ
RAB = 10 kΩ
RAB = 100 kΩ
Code = half scale
Min
8
−2
−5
−1
−2
−0.5
−8
−1
−1
−0.5
−0.5
−2.5
−1
Typ1 Max
±0.2 +2
±1.5 +5
±0.1 +1
±0.5 +2
±0.2 +0.5
±1 +8
35
55 125
130 400
40 80
60 230
±0.2 +1
±0.2 +1
±0.1 +0.5
±0.2 +0.5
−0.1
±0.2 +1
1.2 3
0.5 1
±5
Unit
Bits
LSB
LSB
LSB
LSB
LSB
%
ppm/°C
%
LSB
LSB
LSB
LSB
LSB
LSB
LSB
ppm/°C
Rev. 0 | Page 6 of 32
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AD5142 pdf, datenblatt
AD5122/AD5142
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Data Sheet
GND 1
A1 2
W1 3
B1 4
PIN 1
INDICATOR
AD5122/
AD5142
TOP VIEW
(Not to Scale)
12 SDI
11 SCLK
10 VLOGIC
9 VDD
NOTES
1. INTERNALLY CONNECT THE
EXPOSED PAD TO VSS.
Figure 6. 16-Lead LFCSP Pin Configuration
Table 8. 16-Lead LFCSP Pin Function Descriptions
Pin No. Mnemonic
Description
1 GND
Ground Pin, Logic Ground Reference.
2 A1
3 W1
4 B1
5 VSS
6 A2
7 W2
8 B2
9 VDD
10 VLOGIC
11 SCLK
Terminal A of RDAC1. VSS ≤ VA ≤ VDD.
Wiper Terminal of RDAC1. VSS ≤ VW ≤ VDD.
Terminal B of RDAC1. VSS ≤ VB ≤ VDD.
Negative Power Supply. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors.
Terminal A of RDAC2. VSS ≤ VA ≤ VDD.
Wiper Terminal of RDAC2. VSS ≤ VW ≤ VDD.
Terminal B of RDAC2. VSS ≤ VB ≤ VDD.
Positive Power Supply. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors.
Logic Power Supply; 1.8 V to VDD. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors.
Serial Clock Line. Data is clocked in at the logic low transition.
12 SDI
Serial Data Input.
13 SDO
Serial Data Output. This is an open-drain output pin, and it needs an external pull-up resistor.
14 SYNC
Synchronization Input, Active Low. When SYNC returns high, data is loaded into the input shift register.
15 INDEP
Linear Gain Setting Mode at Power-Up. Each string resistor is loaded independently from its associated
memory location. If INDEP is enabled, it cannot be disabled by software.
16 RESET
EPAD
Hardware Reset Pin. Refresh the RDAC registers from EEPROM. RESET is activated at the logic low. If this pin is
not used, tie RESET to VLOGIC.
Internally Connect the Exposed Pad to VSS.
Rev. 0 | Page 12 of 32
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