Datenblatt-pdf.com


GS9020A Schematic ( PDF Datasheet ) - GENNUM

Teilenummer GS9020A
Beschreibung Serial Digital Video Input Processor
Hersteller GENNUM
Logo GENNUM Logo 




Gesamt 30 Seiten
GS9020A Datasheet, Funktion
*(1/,1; ,, GS9020A
Serial Digital Video Input Processor
FEATURES
• fully compatible with SMPTE 259M
• drop-in replacement for the GS9020
• auto-standard operation to 540MHz
• embedded EDH and data processing core
• selectable loop through or re-serialized EDH-processed
serial output
• noise immune HVF timing signal outputs
• configurable FIFO reset pulse for clearing downstream
FIFOs
• ANC header and TRS-ID correction for all standards
• user controlled output blanking
• ITU-R-601 output clipping for active picture area
• ancillary data indication
• low system power
• selectable I²C interface or 8-bit parallel port for access to
EDH flags and device configuration bits
• EDH flags also available on dedicated pins
• seamless flag mapping to GS9021 EDH coprocessor
• 80 pin LQFP
APPLICATIONS
SMPTE 259M serial digital receiver for composite and
component standards including 4:4:4:4 at 540Mb/s with
EDH processing; Noise immune digital sync and timing
generation; Cost effective EDH insertion and checking for
serial routing and distribution applications.
DESCRIPTION
DATA SHEET
The GS9020A is specifically designed to deserialize SMPTE
259M serial digital signals. The inclusion of Error Detection
and Handling (EDH) ensures the integrity of the data being
received from the serial digital interface (SDI). Internal 75
termination resistors allow INTERLINX™ seamless
connection with the GS9035A Reclocker or the GS9025A
Receiver, thus providing a complete high performance,
digital video input processor with EDH, digital sync signal
generation, and other system features.
The GS9020A also includes a parallel to serial converter
and NRZI scrambler to provide re-serialized, EDH
compliant data output. The EDH core implements EDH
insertion and extraction according to SMPTE RP-165. This
core also generates noise immune timing signals such as
horizontal sync, vertical blanking, field ID and ancillary data
identification. It also provides many system features such
as a FIFO reset pulse (which can be programmed to
coincide with either EAV or SAV), TRS-ID and ANC header
correction, user controlled output blanking and ITU-R-601
output clipping. The GS9020A has an I²C (Inter-Integrated
Circuit, I²C is a registered Trademark of Philips) serial
interface bus and an 8-bit parallel port for external access
to all error flags and device configuration bits.
ORDERING INFORMATION
PART NUMBER
PACKAGE
GS9020ACFV
80 pin LQFP Tray
GS9020ACTV
80 pin LQFP Tape
TEMPERATURE
0°C to 70°C
0°C to 70°C
SDOMODE
SDO
SDO
PARALLEL TO
BUF
0
1
SERIAL
CONVERTER
WITH SCRAMBLER
SDI
BUF
SDI
SCI
BUF
SCI
SERIAL TO
DESCRAMBLER
10
FRAMED
DATA [9:0]
PARALLEL
CONVERTER
SYNC
DETECTOR
PRESSCCRAAMLBELRER
PCLK OUT
RESET
ALIGNING
CONTROL
UNIT
EDH
AND DATA
PROCESSING
CORE
10
5
4
7
BLOCK DIAGRAM
DOUT[9:0]
FIFO_RESET
HVF
CLIP_TRS
ANC_CHKSM
STANDARDS
INDICATOR
HOSTIF
TRS_ERR
DEDICATED
FLAG PORT
PCLKOUT
Revision Date: March 2002
GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3
Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 E-mail: [email protected]
www.gennum.com
Document No. 19922 - 2






GS9020A Datasheet, Funktion
PIN DESCRIPTIONS
NUMBER
SYMBOL
78 CLIP_TRS
79 TRS_ERR
80 ANC_DATA
1, 4, 13
2, 3, 14
69
VDD
GND
SVDD
72 SGND
5, 8 VDD_SDI, SDI
9, 12
VDD_SCI, SCI
29,51,68
30,50,67
VDD
GND
TYPE
DESCRIPTION
I Clip and TRS correction control. When HIGH, the TRS Blanking, ITU-R-601 clipping and TRS
insertion features are enabled.
O TRS error indication. When HIGH, indicates a TRS error in the data stream such as a missing
TRS, an improperly placed TRS, or an incorrect TRS ID word.
O Ancillary data indication. When HIGH, indicates that an ANC packet is coming out of the
device. The output is high from the beginning of the first header word to the end of the
checksum word of the ANC packet.
Power supply connection for the serial processing circuitry (nominally +5V).
Ground connection for the serial processing circuitry.
Power supply connection for the serial data outputs. To save power when not using the SDO/
SDO outputs, set this pin to ground.
Ground connection for the serial data outputs.
Power supply connection for the internal 75 ohm pullup resistor (nominally +5V) on the serial
data input lines.
Power supply connection for the internal 75 ohm pullup resistor (nominally +5V) on the serial
clock input lines.
Power supply connection for the parallel processing circuitry (nominally +5V).
Ground for the parallel processing circuitry.
FRAMED
DATA [9:0]
VBLANKS/L
FLYWDIS
H, V, F
TRS_ ERROR
HOSTIF_MODE FLAG_MAP
EDH FLAG
EXTRACTION
CRC
COMPARISON/
CALCULATION
10
HVF
TRS
5 FLYWHEEL DETECTION
ANCILLARY
CHECKSUM
CALCULATION/
COMPARISON
TRS
COMPARE
ANCILLARY
CHECKSUM
CORRECTION
10
HOST INTERFACE/
FLAG PORT
ERRORED
FIELD
COUNTER
FLAGS
I²C
INTERFACE
DEDICATED
FLAG PORT
8-BIT
PARALLEL
INTERFACE
BYPASS_EDH
ERROR FLAGS 10
& 10
FORMAT PACKET
MUX
DOUT[9:0]
CRC_MODE
NEW CRC
CALCULATION
I²C is a registered
Trademark of Philips
ITU-R-601 CLIPPING
TRS BLANKING
TRS INSERTION/
CORRECTION
10
BLANK_EN CLIP_TRS
BLOCK DIAGRAM - EDH AND DATA CORE PROCESSING
19922 - 2
6

6 Page









GS9020A pdf, datenblatt
3.4 Ancillary Checksum Verification
3.6 ANC_DATA
PIN
ANC_CHKSM
LOGIC OPR
OR
HOST BIT
ANC_CHKSM
EDH_CHKSM
For each received ANC packet in the incoming data, the
device compares the calculated checksum value to the
embedded checksum for that ANC packet. If the
checksum values do not match for any ANC packets within
a field, an error is reported via the ancillary EDH flag in the
EDH packet. In addition, if the ANC_CHKSM input pin or
HOSTIF write table bit is asserted HIGH, the ancillary
checksum correction block is enabled and the checksum in
the ANC packet is replaced with the calculated one. This
update is required to prevent the ANC data error from being
flagged at every downstream EDH chip.
When implementing applications which use the EDH core
(ie. BYPASS_EDH set LOW), ANC_CHKSM will indicate a
downstream FF/AP EDH error when an illegal/non-allowed
(3FCH-3FFH) ANC_CHKSM input value is detected. As
such, these values should not be present in the incoming
data and the corresponding FF/AP EDH errors should not
occur. However, if the user wishes to disable the
ANC_CHKSM function, it can be deactivated by setting
both the ANC_CHSKM pin and the ANC_CHKSM host
interface bit LOW.
If the chip is receiving ANC EDH flag information through
the flag port or the HOSTIF, then the ANC EDH flag
generated by the ancillary checksum verification block will
be overwritten. However, the additional FF/AP EDH flag will
still appear at the next downstream chip if an illegal
checksum of 3FCH-3FFH was detected and the
ANC_CHKSM function was enabled.
If a checksum error is detected in the EDH packet itself, an
additional separate error flag, EDH_CHKSM is set HIGH in
the HOSTIF read table.
3.5 UES Error Flag Updating
In receive mode, a UES flag is set HIGH in the outgoing
EDH packet if the corresponding UES flag was HIGH in the
incoming packet or if the corresponding V bit was LOW.
(For example, if the incoming Active Picture V bit is LOW,
the outgoing Active Picture UES bit will be HIGH). If there is
no EDH packet in the incoming data, all three UES flags
(ANC, AP, FF) are set HIGH.
PIN
ANC_DATA
LOGIC OPR
HOST BIT
The ANC_DATA signal is set HIGH when an ancillary data
packet is exiting the GS9020A. This pin is asserted from the
start of the first header word through to the end of the
checksum word of the ANC packet, inclusive, as shown in
Figure 10.
3.7 NO_EDH
PIN
NO_EDH
LOGIC OPR
HOST BIT
NO_EDH
Some input data streams may lack the EDH packet. In such
cases, the NO_EDH output pin or HOSTIF read table bit is
asserted HIGH. If only a few fields lack the EDH packet, the
NO_EDH pin/bit will be asserted only for those fields.
In determining if the input data stream contains an EDH
packet, the GS9020A looks for two things. First the
presence of an ANC packet with the header 000 3FF 3FF
1F4 and second that the ANC header is in the right spot for
the video standard detected. The NO_EDH signal is a
logical NAND of these two cases. If either one is false, the
NO_EDH flag is set.
3.8 ERRORED FIELD COUNTER
PIN LOGIC OPR
HOST BIT
ERRORED FIELD COUNTER
CLR[1:0]
ERROR SENSITIVITY BITS
The device has a 24 bit ERRORED FIELD COUNTER. The
counter increments by one on the occurrence of one or
more error flags in an OUTGOING EDH packet. The error
flags that can increment the counter are user-selectable
through the 16 ERROR SENSITIVITY bits in the HOSTIF
write table. The error flag SENSITIVITY bits are active LOW,
so that if a particular sensitivity bit is set LOW, the counter is
sensitive to errors of that type in the OUTGOING EDH
packet. The EDH_CHKSM sensitivity bit is active HIGH.
There are four modes of counter operation. The mode is set
through 2 bits in the HOSTIF write table, denoted CLR1 and
CLR0.
19922 - 2
12

12 Page





SeitenGesamt 30 Seiten
PDF Download[ GS9020A Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
GS9020ASerial Digital Video Input ProcessorGENNUM
GENNUM

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche