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A54SX16 Schematic ( PDF Datasheet ) - Actel

Teilenummer A54SX16
Beschreibung SX Family FPGAs
Hersteller Actel
Logo Actel Logo 




Gesamt 30 Seiten
A54SX16 Datasheet, Funktion
SX Family FPGAs
Leading Edge Performance
• 320 MHz Internal Performance
• 3.7 ns Clock-to-Out (Pin-to-Pin)
• 0.1 ns Input Setup
• 0.25 ns Clock Skew
Specifications
• 12,000 to 48,000 System Gates
• Up to 249 User-Programmable I/O Pins
• Up to 1,080 Flip-Flops
• 0.35 µ CMOS
SX Product Profile
Device
Capacity
Typical Gates
System Gates
Logic Modules
Combinatorial Cells
Register Cells (Dedicated Flip-Flops)
Maximum User I/Os
Clocks
JTAG
PCI
Clock-to-Out
Input Setup (external)
Speed Grades
Temperature Grades
Packages (by pin count)
PLCC
PQFP
VQFP
TQFP
PBGA
FBGA
A54SX08
8,000
12,000
768
512
256
130
3
Yes
3.7 ns
0.8 ns
Std, –1, –2, –3
C, I, M
84
208
100
144, 176
144
v3.2
ue
Features
• 66 MHz PCI
• CPLD and FPGA Integration
• Single-Chip Solution
• 100% Resource Utilization with 100% Pin Locking
• 3.3 V and 5.0 V Operation with 5.0 V Input Tolerance
• Very Low Power Consumption
• Deterministic, User-Controllable Timing
• Unique In-System Diagnostic and Debug Capability
with Silicon Explorer II
• Boundary Scan Testing in Compliance with IEEE
Standard 1149.1 (JTAG)
• Secure Programming Technology Prevents Reverse
Engineering and Design Theft
A54SX16
16,000
24,000
1,452
924
528
175
3
Yes
3.9 ns
0.5 ns
Std, –1, –2, –3
C, I, M
208
100
176
A54SX16P
16,000
24,000
1,452
924
528
175
3
Yes
Yes
4.4 ns
0.5 ns
Std, –1, –2, –3
C, I, M
208
100
144, 176
A54SX32
32,000
48,000
2,880
1,800
1,080
249
3
Yes
4.6 ns
0.1 ns
Std, –1, –2, –3
C, I, M
208
144, 176
313, 329
June 2006
© 2006 Actel Corporation
i
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A54SX16 Datasheet, Funktion
SX Family FPGAs
The R-cell contains a flip-flop featuring asynchronous
clear, asynchronous preset, and clock enable (using the
S0 and S1 lines) control signals (Figure 1-2). The R-cell
registers feature programmable clock polarity selectable
on a register-by-register basis. This provides additional
flexibility while allowing mapping of synthesized
functions into the SX FPGA. The clock source for the
R-cell can be chosen from either the hardwired clock or
the routed clock.
Routing Tracks
Metal 3
Metal 2
Amorphous Silicon/
Dielectric Antifuse
Tungsten Plug Via
Tungsten Plug Via
Metal 1
Tungsten Plug
Contact
Silicon Substrate
Figure 1-1 • SX Family Interconnect Elements
Routed Data Input
S0 S1
PSETB
Direct
Connect
Input
DQ
Y
HCLK
Figure 1-2 • R-Cell
CLKA, CLKB,
Internal Logic
CKS
CLRB
CKP
The C-cell implements a range of combinatorial functions
up to 5-inputs (Figure 1-3 on page 1-3). Inclusion of the
DB input and its associated inverter function dramatically
increases the number of combinatorial functions that can
be implemented in a single module from 800 options in
previous architectures to more than 4,000 in the SX
architecture. An example of the improved flexibility
enabled by the inversion capability is the ability to
integrate a 3-input exclusive-OR function into a single
C-cell. This facilitates construction of 9-bit parity-tree
functions with 2 ns propagation delays. At the same
time, the C-cell structure is extremely synthesis friendly,
simplifying the overall design and reducing synthesis
time.
1-2 v3.2
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6 Page









A54SX16 pdf, datenblatt
SX Family FPGAs
Table 1-4 • Recommended Operating Conditions
Parameter
Commercial
Industrial
Military
Temperature Range*
0 to + 70
–40 to + 85
–55 to +125
3.3 V Power Supply Tolerance
±10
±10
±10
5.0 V Power Supply Tolerance
±5
±10
±10
Note: *Ambient temperature (TA) is used for commercial and industrial; case temperature (TC) is used for military.
Units
°C
%VCC
%VCC
Table 1-5 • Electrical Specifications
Symbol
VOH
VOL
VIL
VIH
tR, tF
CIO
ICC
ICC(D)
Parameter
(IOH = –20 µA) (CMOS)
(IOH = –8 mA) (TTL)
(IOH = –6 mA) (TTL)
(IOL= 20 µA) (CMOS)
(IOL = 12 mA) (TTL)
(IOL = 8 mA) (TTL)
Input Transition Time tR, tF
CIO I/O Capacitance
Standby Current, ICC
ICC(D) IDynamic VCC Supply Current
Commercial
Industrial
Min.
Max.
Min.
Max.
Units
(VCCI – 0.1)
2.4
VCCI
VCCI
0.10
0.50
(VCCI – 0.1)
2.4
VCCI
VCCI
0.50
V
V
0.8 0.8 V
2.0 2.0
V
50 50 ns
10 10 pF
4.0 4.0 mA
See "Evaluating Power in SX Devices" on page 1-16.
1-8 v3.2
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