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AD5504 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD5504
Beschreibung Quad-Channel 12-Bit Voltage Output DAC
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 20 Seiten
AD5504 Datasheet, Funktion
Data Sheet
High Voltage, Quad-Channel
12-Bit Voltage Output DAC
AD5504
FEATURES
Quad-channel high voltage DAC
12-bit resolution
Pin selectable 30 V or 60 V output range
Integrated precision reference
Low power serial interface with readback capability
Integrated temperature sensor alarm function
Power-on reset
Simultaneous updating via LDAC
Wide operating temperature: −40°C to +105°C
APPLICATIONS
Programmable voltage sources
High voltage LED drivers
Receiver bias in optical communications
GENERAL DESCRIPTION
The AD5504 is a quad-channel, 12-bit, serial input, digital-to-
analog converter with on-chip high voltage output amplifiers
and an integrated precision reference. The DAC output voltage
ranges are programmable via the range select pin (R_SEL). If
R_SEL is held high, the DAC output ranges are 0 V to 30 V. If
R_SEL is held low, the DAC output ranges are 0 V to 60 V. The
on-chip output amplifiers allow an output swing within the
range of AGND + 0.5 V to VDD − 0.5 V.
The AD5504 has a high speed serial interface, which is com-
patible with SPI®-, QSPI™-, MICROWIRE™-, and DSP-interface
standards and can handle clock speeds of up to 16.667 MHz.
CLR R_SEL VLOGIC
FUNCTIONAL BLOCK DIAGRAM
LDAC
VDD
SDI
SDO
SCLK
SYNC
ALARM
REFERENCE
1713kΩ
122.36kΩ
INPUT
DAC
REGISTER
REGISTER
DACA
12 A
A 12
+
1713kΩ
INPUT
CONTROL
LOGIC
122.36kΩ
INPUT
REGISTER
B
DAC
REGISTER
B
12
DAC B
+
1713kΩ
POWER-ON
RESET
INPUT
REGISTER
C
DAC
REGISTER
C
12
122.36kΩ
DAC C
+
1713kΩ
INPUT
REGISTER
D
DAC
REGISTER
D
12
122.36kΩ
DAC D
+
VOUTA
VOUTB
VOUTC
VOUTD
AD5504
DGND
Figure 1.
POWER-DOWN
CONTROL LOGIC
TEMPERATURE
SENSOR
AGND
Rev. B
Document Feedback
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responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2009-2012 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
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AD5504 Datasheet, Funktion
AD5504
Data Sheet
TIMING CHARACTERISTICS
VDD = 30 V, VLOGIC = 2.3 V to 5.5 V and −40°C < TA < +105°C; all specifications TMIN to TMAX, unless otherwise noted.
Table 4.
Parameter
t1 2
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t153
t163
t174
t185
t19
Limit1
60
10
10
25
15
5
0
20
20
50
15
100
20
110
55
25
50
50
5
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns typ
μs typ
ns min
ns max
ns min
μs max
μs max
μs typ
Test Conditions/Comments
SCLK cycle time
SCLK high time
SCLK low time
SYNC falling edge to SCLK rising edge setup time
Data setup time
Data hold time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time
LDAC pulse width low
SCLK falling edge to LDAC rising edge
CLR pulse width low
CLR pulse activation time
ALARM clear time
SCLK cycle time in read mode
SCLK rising edge to SDO valid
SCLK to SDO data hold time
Power-on reset time (this is not shown in the timing diagrams)
Power-on time (this is not shown in the timing diagrams)
ALARM clear to output amplifier turn on (this is not shown in the timing
diagrams)
1 All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
2 Maximum SCLK frequency is 16.667 MHz.
3 Under load conditions shown in Figure 2.
4 Time from when the VDD/VLOGIC supplies are powered-up to when a digital interface command can be executed.
5 Time required from execution of power-on software command to when the DAC outputs have settled to 1 V.
200µA
IOL
TO OUTPUT
PIN CL
50pF
VOH (MIN) – VOL (MAX)
2
200µA
IOH
Figure 2. Load Circuit for SDO Timing Diagram
Rev. B | Page 6 of 20
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AD5504 pdf, datenblatt
AD5504
TERMINOLOGY
Relative Accuracy
For the DAC, relative accuracy, or integral nonlinearity (INL),
is a measure of the maximum deviation in LSBs from a straight
line passing through the endpoints of the DAC transfer function.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between the
measured change and the ideal 1 LSB change between any two
adjacent codes. A specified differential nonlinearity of ±1 LSB
maximum ensures monotonicity. This DAC is guaranteed mono-
tonic by design.
Zero-Code Error
Zero-code error is a measure of the output error when zero
code (0x000) is loaded into the DAC register. Ideally, the output
should be 0 V. The zero-code error is always positive in the
AD5504 because the output of the DAC cannot go below 0 V.
It is due to a combination of the offset errors in the DAC and
output amplifier. Zero-code error is expressed in millivolts.
Zero-Code Error Drift
Zero-code error drift is a measure of the change in zero-code
error with a change in temperature. It is expressed in μV/°C.
Offset Error
A measure of the difference between VOUT (actual) and VOUT
(ideal) expressed in millivolts in the linear region of the transfer
function. Offset error is measured on the AD5504 with Code 32
loaded in the DAC registers for 60 V mode and with Code 64
loaded in the DAC registers for 30 V mode. Offset error is
expressed in millivolts.
Offset Error Drift
Offset error drift is a measure of the change in offset error with
a change in temperature. It is expressed in μV/°C.
Full-Scale Error
Full-scale error is a measure of the output error when full-scale
code (0xFFF) is loaded into the DAC register. Full-scale error is
expressed in millivolts.
Full-Scale Error Drift
Full-scale error drift is a measure of the change in full-scale
error with a change in temperature. It is expressed in μV/°C.
Gain Error
Gain error is a measure of the span error of the DAC. It is the
deviation in slope of the DAC transfer characteristic from the
ideal, expressed as a percentage of the full-scale range.
Data Sheet
Gain Temperature Coefficient
The gain temperature coefficient is a measure of the change in
gain with changes in temperature. It is expressed in (ppm of
full-scale range)/°C.
Digital-to-Analog Glitch Impulse
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV-s
and is measured when the digital input code is changed by
1 LSB at the major carry transition.
DC and AC Power Supply Rejection Ratio (PSRR)
PSRR indicates how the output of the DAC is affected by changes
in the supply voltage. PSRR is the ratio of the change in VOUTA,
VOUTB, VOUTC, or VOUTD to a change in VDD for full-scale output of
the DAC. It is measured in decibels. For dc PSRR, VDD is dc
varied ±10%. For ac PSRR, VDD is ac varied ±10%.
DC Crosstalk
DC crosstalk is the dc change in the output level of one DAC in
response to a change in the output of another DAC. It is measured
with a full-scale output change on one DAC (or soft power-down
and power-up) while monitoring another DAC kept at midscale.
It is expressed in millivolts.
DC crosstalk due to load current change is a measure of the
impact that a change in load current on one DAC has to another
DAC kept at midscale. It is expressed in μV/mA.
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into
the analog output of a DAC from the digital input pins of the
device but is measured when the DAC is not being written to
(SYNC held high). It is specified in nV-s and measured with a
full-scale change on the digital input pins, that is, from all 0s to
all 1s or vice versa.
Analog Crosstalk
Analog crosstalk is the glitch impulse transferred to the output
of one DAC due to a change in the output of another DAC. It is
measured by loading one of the input registers with a full-scale
code change (all 0s to all 1s or vice versa) while keeping LDAC
high, and then pulsing LDAC low and monitoring the output of
the DAC whose digital code has not changed. The area of the
glitch is expressed in nV-s.
Rev. B | Page 12 of 20
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