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PDF ADRF6750 Data sheet ( Hoja de datos )
| Número de pieza | ADRF6750 | |
| Descripción | 950 MHz to 1575 MHz Quadrature Modulator | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ADRF6750 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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950 MHz to 1575 MHz Quadrature Modulator
with Integrated Fractional-N PLL and VCO
ADRF6750
FEATURES
I/Q modulator with integrated fractional-N PLL and VCO
Gain control span: 47 dB in 1 dB steps
Output frequency range: 950 MHz to 1575 MHz
Output 1 dB compression: 8.5 dBm
Output IP3: 23 dBm
Noise floor: −162 dBm/Hz
Baseband modulation bandwidth: 250 MHz (1 dB)
Output frequency resolution: 1 Hz
Functions with external VCO for extended frequency range
SPI and I2C-compatible serial interfaces
Power supply: 5 V/310 mA
GENERAL DESCRIPTION
The ADRF6750 is a highly integrated quadrature modulator,
frequency synthesizer, and programmable attenuator. The
device covers an operating frequency range from 950 MHz
to 1575 MHz for use in satellite, cellular and broadband
communications.
The ADRF6750 modulator includes a high modulus fractional-N
frequency synthesizer with integrated VCO, providing better
than 1 Hz frequency resolution, and a 47 dB digitally controlled
output attenuator with 1 dB steps.
Control of all the on-chip registers is through a user-selected
SPI interface or I2C interface. The device operates from a single
power supply ranging from 4.75 V to 5.25 V.
REGOUT
VREG1
VREG2
VREG3
VREG4
VREG5
VREG6
LOMONP
LOMONN
RFOUT
TXDIS
FUNCTIONAL BLOCK DIAGRAM
VCC1 VCC2 VCC3 VCC4
3.3V
REGULATOR
47dB
GAIN CONTROL
RANGE
0°/90°
OUTPUT
STAGE
VCO
CORE
REFIN
REFIN
×2
DOUBLER
SDI/SDA
CLK/SCL
SDO
CS
SPI/
I2C
INTERFACE
ADRF6750
5-BIT
DIVIDER
÷2
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
+ PHASE
FREQUENCY
– DETECTOR
REFERENCE
CHARGE
PUMP
N-COUNTER
CURRENT SETTING
RFCP4 RFCP3 RFCP2 RFCP1
FRACTIONAL MODULUS
REGISTER
225
INTEGER
REGISTER
AGND
DGND
Figure 1.
IBBP
IBBN
CCOMP1
CCOMP2
CCOMP3
VTUNE
TESTLO
TESTLO
QBBP
QBBN
RSET
CP
LF3
LF2
LDET
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2010 Analog Devices, Inc. All rights reserved.
Free Datasheet http://www.datasheet4u.com/
1 page  
TIMING CHARACTERISTICS
I2C Interface Timing
Table 2.
Parameter1
SCL Clock Frequency
SCL Pulse Width High
SCL Pulse Width Low
Start Condition Hold Time
Start Condition Setup Time
Data Setup Time
Data Hold Time
Stop Condition Setup Time
Data Valid Time
Data Valid Acknowledge Time
Bus Free Time
1 See Figure 2.
Symbol
fSCL
tHIGH
tLOW
tHD;STA
tSU;STA
tSU;DAT
tHD;DAT
tSU;STO
tVD;DAT
tVD;ACK
tBUF
SDA
SCL
S
START
CONDITION
tSU;DAT
tHD;STA
tLOW
1/fSCL
tHD;DAT
ADRF6750
Limit
400
600
1300
600
600
100
300
600
900
900
1300
ttVVDD;;DAACTK
AND
(ACK
SIGNAL
ONLY)
tSU;STA
tSU;STO
Unit
kHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns min
tBUF
tHIGH
S
Figure 2. I2C Port Timing Diagram
P
STOP
CONDITION
S
Rev. A | Page 5 of 40
Free Datasheet http://www.datasheet4u.com/
5 Page 
60
NOMINAL
50 WORST-CASE
40
30
20
10
0
–80 –75 –70 –65 –60 –55 –50 –45 –40 –35 –30
LO CARRIER FEEDTHROUGH (dBc)
Figure 11. LO Carrier Feedthrough Distribution at Nominal and Worst-Case
Conditions and Attenuation Setting
–40
–50
–60
–70
–80
–90
–100
–110
–120
ATTENUATION = 0dB
ATTENUATION = 12dB
ATTENUATION = 21dB
ATTENUATION = 33dB
ATTENUATION = 47dB
LO FREQUENCY (MHz)
Figure 12. 2 × LO Carrier Feedthrough vs. Attenuation, LO Frequency,
Supply, and Temperature
10 1.0
5 0.5
1dB
0 COMPRESSION 0
POINT
–5 –0.5
–10 –1.0
–15 –1.5
–20 –2.0
–25
0.1
1
DIFFERENTIAL INPUT VOLTAGE (V p-p)
–2.5
10
Figure 13. Output P1dB Compression Point at Worst-Case LO Frequency
vs. Supply and Temperature
ADRF6750
50
NOMINAL
45 WORST-CASE
40
35
30
25
20
15
10
5
0
6.8 7.0 7.2 7.4 7.6 7.8 8.0 8.2 8.4 8.6 8.8 9.0 9.2
OUTPUT P1dB (dBm)
Figure 14. Output P1dB Compression Point Distribution at Nominal
and Worst-Case Conditions
10.5
10.0
9.5
9.0
8.5
8.0
7.5
7.0
6.5
6.0
LO FREQUENCY (MHz)
Figure 15. Output P1dB Compression Point vs. LO Frequency at
Nominal Conditions
45
NOMINAL
40
WORST-CASE
35
30
25
20
15
10
5
0
OUTPUT IP3 (dBm)
Figure 16. Output IP3 Distribution at Nominal and Worst-Case
Conditions
Rev. A | Page 11 of 40
Free Datasheet http://www.datasheet4u.com/
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ADRF6750.PDF ] | |
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