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ADF4157 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADF4157
Beschreibung High Resolution 6 GHz Fractional-N Frequency Synthesizer
Hersteller Analog Devices
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Gesamt 25 Seiten
ADF4157 Datasheet, Funktion
Data Sheet
High Resolution 6 GHz Fractional-N
Frequency Synthesizer
ADF4157
FEATURES
GENERAL DESCRIPTION
RF bandwidth to 6 GHz
25-bit fixed modulus allows subhertz frequency resolution
2.7 V to 3.3 V power supply
Separate VP allows extended tuning voltage
Programmable charge pump currents
3-wire serial interface
Digital lock detect
Power-down mode
Pin compatible with the following frequency synthesizers:
ADF4110/ADF4111/ADF4112/ADF4113/
ADF4106/ADF4153/ADF4154/ADF4156
Cycle slip reduction for faster lock times
APPLICATIONS
The ADF4157 is a 6 GHz fractional-N frequency synthesizer with
a 25-bit fixed modulus, allowing subhertz frequency resolution
at 6 GHz. It consists of a low noise digital phase frequency detector
(PFD), a precision charge pump, and a programmable reference
divider. There is a Σ-Δ based fractional interpolator to allow
programmable fractional-N division. The INT and FRAC values
define an overall N divider, N = INT + (FRAC/225). The ADF4157
features cycle slip reduction circuitry, which leads to faster lock
times without the need for modifications to the loop filter.
Control of all on-chip registers is via a simple 3-wire interface.
The device operates with a power supply ranging from 2.7 V to
3.3 V and can be powered down when not in use.
Satellite communications terminals, radar equipment
Instrumentation equipment
Personal mobile radio (PMR)
Base stations for mobile radio
Wireless handsets
FUNCTIONAL BLOCK DIAGRAM
AVDD DVDD VP
RSET
ADF4157
REFIN
MUXOUT
CE
×2
DOUBLER
5-BIT
R COUNTER
÷2
DIVIDER
HIGH Z
OUTPUT
MUX
VDD
DGND
SDOUT
VDD
RDIV
NDIV
LOCK
DETECT
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
REFERENCE
+ PHASE
FREQUENCY
DETECTOR
CHARGE
PUMP
CURRENT
SETTING
CSR
CP
RFCP4 RFCP3 RFCP2 RFCP1
N COUNTER
RFINA
RFINB
CLK
DATA
LE
32-BIT
DATA
REGISTER
FRACTION MODULUS
REG
225
INTEGER
REG
AGND
DGND
Figure 1.
CPGND
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2007–2012 Analog Devices, Inc. All rights reserved.






ADF4157 Datasheet, Funktion
Data Sheet
ADF4157
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, GND = AGND = DGND = 0 V, VDD = AVDD = DVDD, unless otherwise noted.
Table 3.
Parameter
AVDD/DVDD to AGND/DGND
AVDD to DVDD
VP to AGND/DGND
VP to AVDD/DVDD
Digital I/O Voltage to AGND/DGND
Analog I/O Voltage to AGND/DGND
REFIN, RFINx to AGND/DGND
Operating Temperature Range
Industrial (B Version)
Storage Temperature Range
Maximum Junction Temperature
Reflow Soldering
Peak Temperature
Time at Peak Temperature
Rating
−0.3 V to +4 V
−0.3 V to +0.3 V
−0.3 V to +5.8 V
−0.3 V to +5.8 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−40°C to +85°C
−65°C to +125°C
150°C
260°C
40 sec
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 4. Thermal Resistance
Package Type
TSSOP
LFCSP (Paddle Soldered)
θJA
112
30.4
Unit
°C/W
°C/W
ESD CAUTION
Rev. D | Page 5 of 24

6 Page









ADF4157 pdf, datenblatt
Data Sheet
ADF4157
REGISTER MAPS
FRAC/INT REGISTER (R0)
MUXOUT
CONTROL
12-BIT INTEGER VALUE (INT)
12-BIT MSB FRACTIONAL VALUE
(FRAC)
CONTROL
BITS
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 M4 M3 M2 M1 N12 N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 C3(0) C2(0) C1(0)
LSB FRAC REGISTER (R1)
RESERVED
13-BIT LSB FRACTIONAL VALUE
(FRAC) (DBB)
RESERVED
CONTROL
BITS
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 0 0 0 0 0 0 0 0 0 0 0 0 C3(0) C2(0) C1(1)
DBB
CURRENT
SETTING
R DIVIDER REGISTER (R2)
DBB
5-BIT R COUNTER
RESERVED
CONTROL
BITS
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 C1 CPI4 CPI3 CPI2 CPI1 0 P1 U2 U1 R5 R4 R3 R2 R1 0 0 0 0 0 0 0 0 0 0 0 0 C3(0) C2(1) C1(0)
FUNCTION REGISTER (R3)
RESERVED
RESERVED
CONTROL
BITS
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 U12 0 0 0 0 0 0 U11 U10 U9 U8 U7 C3(0) C2(1) C1(1)
TEST REGISTER (R4)
RESERVED
CLK
DIV
MODE
12-BIT CLOCK DIVIDER VALUE
RESERVED
CONTROL
BITS
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 0 0 0 NB2 NB1 0 0 C2 C1 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 0 0 0 0 C3(1) C2(0) C1(0)
NOTES
1. DBB = DOUBLE BUFFERED BIT(S).
Figure 16. Register Summary
Rev. D | Page 11 of 24

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