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PDF ADAU1442 Data sheet ( Hoja de datos )
| Número de pieza | ADAU1442 | |
| Descripción | SigmaDSP Digital Audio Processor | |
| Fabricantes | Analog Devices | |
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SigmaDSP Digital Audio Processor
with Flexible Audio Routing Matrix
ADAU1442/ADAU1445/ADAU1446
FEATURES
Fully programmable audio digital signal processor (DSP) for
enhanced sound processing
Features SigmaStudio, a proprietary graphical programming
tool for the development of custom signal flows
172 MHz SigmaDSP core; 3584 instructions per sample at 48 kHz
4k parameter RAM, 8k data RAM
Flexible audio routing matrix (FARM)
24-channel digital input and output
Up to 8 stereo asynchronous sample rate converters
(from 1:8 up to 7.75:1 ratio and 139 dB DNR)
Stereo S/PDIF input and output
Supports serial and TDM I/O, up to fS = 192 kHz
Multichannel byte-addressable TDM serial port
Pool of 170 ms digital audio delay (at 48 kHz)
Clock oscillator for generating master clock from crystal
PLL for generating core clock from common audio clocks
I2C and SPI control interfaces
Standalone operation
Self-boot from serial EEPROM
4-channel, 10-bit auxiliary control ADC
Multipurpose pins for digital controls and outputs
Easy implementation of available third-party algorithms
On-chip regulator for generating 1.8 V from 3.3 V supply
100-lead TQFP and LQFP packages
Temperature range: −40°C to +105°C
APPLICATIONS
Automotive audio processing
Head units
Navigation systems
Rear-seat entertainment systems
DSP amplifiers (sound system amplifiers)
Commercial audio processing
FUNCTIONAL BLOCK DIAGRAM
MP[3:0]/
SPI/I2C* SELFBOOT MP[11:4] ADC[3:0]
XTALI XTALO
ADAU1442/
ADAU1445/
ADAU1446
1.8V
REGULATOR
I2C/SPI CONTROL
INTERFACE
AND SELF-BOOT
MP/
AUX ADC
CLOCK
PLL OSCILLATOR
CLKOUT
SPDIFI
S/PDIF
RECEIVER
PROGRAMMABLE AUDIO
PROCESSOR CORE
S/PDIF
TRANSMITTER
SPDIFO
SDATA_IN[8:0]
(24-CHANNEL
DIGITAL AUDIO
INPUT)
BIT CLOCK†
(BCLK)
FRAME CLOCK†
(LRCLK)
FLEXIBLE AUDIO ROUTING MATRIX
(FARM)
SERIAL DATA
INPUT PORT
(×9)
UP TO 16 CHANNELS OF
ASYNCHRONOUS
SAMPLE RATE
CONVERTERS
SERIAL DATA
OUTPUT PORT
(×9)
SERIAL CLOCK
DOMAINS
(×12)
SDATA_OUT[8:0]
(24-CHANNEL
DIGITAL AUDIO
OUTPUT)
BIT CLOCK†
(BCLK)
FRAME CLOCK†
(LRCLK)
*SPI/I2C = THE ADDR0, CLATCH, SCL/CCLK, SDA/COUT, AND ADDR1/CDATA PINS.
†THERE ARE 12 BIT CLOCKS (BCLK[11:0]) AND 12 FRAME CLOCKS (LRCLK[11:0]) IN TOTAL. OF THE 12 CLOCKS,
SIX ARE ASSIGNABLE, THREE MUST BE OUTPUTS, AND THREE MUST BE INPUTS.
Figure 1.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2010 Analog Devices, Inc. All rights reserved.
Free Datasheet http://www.datasheet4u.com/
1 page  
ADAU1442/ADAU1445/ADAU1446
SPECIFICATIONS
AVDD = 3.3 V, DVDD = 1.8 V, PVDD = 3.3 V, IOVDD = 3.3 V, TA = 25°C, master clock input = 12.288 MHz, core clock fCORE = 172.032 MHz,
I/O pins set to 2 mA drive setting, unless otherwise noted.
Table 2.
Parameter
ANALOG PERFORMANCE
Auxiliary Analog Inputs
Resolution
Full-Scale Analog Input
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
Gain Error
Input Impedance
Sample Rate
Min
−2.3
−2.0
−2.0
POWER
Supply Voltage
Analog Voltage (AVDD)
Digital Voltage (DVDD)
PLL Voltage (PVDD)
IOVDD Voltage (IOVDD)
Supply Current
Analog Current (AVDD)
PLL Current (PVDD)
I/O Current (IOVDD)
2.97
1.62
2.97
2.97
Digital Current (DVDD)
ADAU1442
Typical Program
Minimal Program
ADAU1445
Typical Program
Minimal Program
ADAU1446
Typical Program
Minimal Program
ASYNCHRONOUS SAMPLE RATE
CONVERTERS1
Dynamic Range
I/O Sample Rate
6
Typ Max
10
AVDD
200
fCORE/896
+2.3
+2.0
+2.0
3.3 3.63
1.8 1.98
3.3 3.63
3.3 3.63
2
10
10
335
115
270
115
135
110
139
Rev. C | Page 5 of 92
192
Unit Test Conditions/Comments
AVDD = 3.3 V ± 10%.
Bits
V
LSB
LSB
LSB
kΩ
kHz 4:1 multiplexed input, each
channel at fCORE/3584. For
fCORE = 172.032 MHz, each
channel is sampled at 48 kHz.
V
V
V
V
mA
mA
mA Depends greatly on the num-
ber of active serial ports, clock
pins, and characteristics of
external loads.
mA Test program includes
16 channels I/O, 10-band EQ
per channel, all ASRCs active.
mA Test program includes
2 channels I/O, 10-band EQ
per channel.
mA Test program includes
16 channels I/O, 10-band EQ
per channel, all ASRCs active.
mA Test program includes
2 channels I/O, 10-band EQ
per channel.
mA Test program includes
16 channels I/O, 10-band EQ
per channel, all ASRCs active.
Test program includes
2 channels I/O, 10-band EQ
per channel.
dB A-weighted, 20 Hz to 20 kHz.
kHz
Free Datasheet http://www.datasheet4u.com/
5 Page 
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter
DVDD to Ground
AVDD to Ground
IOVDD to Ground
Digital Inputs
Maximum Ambient Temperature
Maximum Junction Temperature
Storage Temperature Range
Soldering (10 sec)
Rating
0 V to 2.2 V
0 V to 4.0 V
0 V to 4.0 V
DGND – 0.3 V to IOVDD + 0.3 V
−40°C to +105°C
150°C
−65°C to +150°C
300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ADAU1442/ADAU1445/ADAU1446
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 6. Thermal Resistance
Package Type
100-Lead TQFP
100-Lead LQFP
θJA
26.3
41.4
θJC
9.4
9.5
Unit
°C/W
°C/W
ESD CAUTION
Rev. C | Page 11 of 92
Free Datasheet http://www.datasheet4u.com/
11 Page | ||
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| PDF Descargar | [ Datasheet ADAU1442.PDF ] | |
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