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AD8186 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD8186
Beschreibung (AD8186 / AD8187) 480 MHz Single-Supply (5V) Triple 2:1 Multiplexers
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 20 Seiten
AD8186 Datasheet, Funktion
a
FEATURES
Fully Buffered Inputs and Outputs
Fast Channel-to-Channel Switching: 4 ns
Single-Supply Operation (5 V)
High Speed:
480 MHz Bandwidth (–3 dB) 2 V p-p
>1600 V/s (G = +1)
>1500 V/s (G = +2)
Fast Settling Time of 7 ns to 0.1%
Low Current: 19 mA/20 mA
Excellent Video Specifications (RL = 150 )
0.05% Differential Gain Error
0.05؇ Differential Phase Error
Low Glitch
All Hostile Crosstalk
–84 dB @ 5 MHz
–52 dB @ 100 MHz
High Off Isolation of –95 dB @ 5 MHz
Low Cost
Fast, High Impedance Disable Feature for Connecting
Multiple Outputs
Logic-Shifted Outputs
APPLICATIONS
Switching RGB in LCD and Plasma Displays
RGB Video Switchers and Routers
GENERAL DESCRIPTION
The AD8186 (G = +1) and AD8187 (G = +2) are high speed,
single-supply, triple 2-to-1 multiplexers. They offer –3 dB large signal
bandwidth of over 480 MHz along with a slew rate in excess of
1500 V/µs. With better than –80 dB of all hostile crosstalk and
–95 dB OFF isolation, they are suited for many high speed appli-
cations. The differential gain and differential phase error of 0.05%
and 0.05°, along with 0.1 dB flatness to 85 MHz, make the
AD8186 and AD8187 ideal for professional and component video
multiplexing. They offer 4 ns switching time, making them an
excellent choice for switching video signals while consuming less
than 20 mA on a single 5 V supply (100 mW). Both devices have a
high speed disable feature that sets the outputs into a high
impedance state. This allows the building of larger input arrays
while minimizing OFF channel output loading. The devices are
offered in a 24-lead TSSOP package.
480 MHz Single-Supply (5 V)
Triple 2:1 Multiplexers
AD8186/AD8187
FUNCTIONAL BLOCK DIAGRAM
IN0A 1
DGND 2
IN1A 3
VREF 4
IN2A 5
VCC 6
VEE 7
IN2B 8
VEE 9
IN1B 10
VEE 11
IN0B 12
LOGIC
24 VCC
23 OE
SELECT
0
ENABLE
22 SEL A/B
21 VCC
20 OUT 0
19 VEE
1 18 OUT 1
17 VCC
2 16 OUT 2
15 VEE
14 DVCC
AD8186/AD8187 13 VCC
Table I. Truth Table
SEL A/B OE OUT
0 0 High Z
1 0 High Z
1 1 IN A
0 1 IN B
4.0 6.0
3.5 5.5
3.0 5.0
2.5 INPUT
4.5
2.0 4.0
1.5 3.5
1.0 3.0
0.5 OUTPUT
2.5
0 2.0
–0.5
–1.0
0
1.5
1.0
5 10 15 20 25
TIME (ns)
Figure 1. AD8187 Video Amplitude Pulse
Response, VOUT = 1.4 V p-p, RL = 150
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved.
Free Datasheet http://www.datasheet4u.com/






AD8186 Datasheet, Funktion
AD8186/AD8187
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
0.1
1 10 100
FREQUENCY (MHz)
1000
TPC 7. AD8186 All Hostile Crosstalk* vs. Frequency
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
0.1
1.0 10.0 100.0
FREQUENCY (MHz)
1000.0
TPC 10. AD8187 All Hostile Crosstalk* vs. Frequency
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
0.1
1.0
10.0
100.0
FREQUENCY (MHz)
1000.0
TPC 8. AD8186 Adjacent Channel Crosstalk* vs. Frequency
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0.1
1.0 10.0 100.0
FREQUENCY (MHz)
1000.0
TPC 11. AD8187 Adjacent Channel Crosstalk* vs. Frequency
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
10 100
FREQUENCY (MHz)
1000
TPC 9. AD8186 OFF Isolation* vs. Frequency
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
1
10 100
FREQUENCY (MHz)
1000
TPC 12. AD8187 OFF Isolation* vs. Frequency
* All hostile crosstalk—Drive all INA, listen to output with INB selected.
Adjacent channel crosstalk—Drive one INA, listen to an adjacent output with INB selected.
Off isolation—Drive inputs with OE tied low.
–6–
REV. A
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AD8186 pdf, datenblatt
AD8186/AD8187
THEORY OF OPERATION
The AD8186 (G = +1) and AD8187 (G = +2) are single-supply,
triple 2:1 multiplexers with TTL compatible global input switch-
ing and output-enable control. Optimized for selecting between
two RGB (red, green, blue) video sources, the devices have high
peak slew rates, maintaining their bandwidth for large signals.
Additionally, the multiplexers are compensated for high phase
margin, minimizing overshoot for good pixel resolution. The
multiplexers also have respectable video specifications and are
superior for switching NTSC or PAL composite signals.
The multiplexers are organized as three independent channels,
each with two input transconductance stages and one output
transimpedance stage. The appropriate input transconductance
stages are selected via one logic pin (SEL A/B) such that all
three outputs switch input connections simultaneously. The
unused input stages are disabled with a proprietary clamp cir-
cuit to provide excellent crosstalk isolation between “on” and
“off ” inputs while protecting the disabled devices from damag-
ing reverse base-emitter voltage stress. No additional input
buffering is necessary, resulting in low input capacitance and
high input impedance without additional signal degradation.
The transconductance stage, a high slew rate, class AB circuit,
sources signal current into a high impedance node. Each output
stage contains a compensation network and is buffered to the
output by a complementary emitter-follower stage. Voltage
feedback sets the gain, with the AD8186 configured as a unity
gain follower and the AD8187 as a gain-of-two amplifier with a
feedback network. This architecture provides drive for a reverse-
terminated video load (150 ) with low differential gain and
phase errors while consuming relatively little power. Careful
chip layout and biasing result in excellent crosstalk isolation
between channels.
High Impedance, Output Disable Feature, and Off Isolation
The output-enable logic pin (OE) controls whether the three
outputs are enabled or disabled to a high impedance state.
The high impedance disable allows larger matrices to be built
by busing the outputs together. In the case of the AD8187
(G = +2), a feedback isolation scheme is used so that the
impedance of the gain-of-two feedback network does not load
the output. When not in use, the outputs can be disabled to
reduce power consumption.
The reader may have noticed that the off isolation performance of
the signal path is dependent upon the value of the load resistor,
RL. For calculating off isolation, the signal path may be modeled
as a simple high-pass network with an effective capacitance of
3 fF. Off isolation will improve as the load resistance is decreased. In
the case of the AD8186, off isolation is specified with a 1 k
load. However, a practical application would likely gang the
outputs of multiple muxes. In this case, the proper load resistance
for the off isolation calculation is the output impedance of an
enabled AD8186, typically less than a 10th of an ohm.
Full Power Bandwidth vs. –3 dB Large Signal Bandwidth
Note that full power bandwidth for an undistorted sinusoidal signal
is often calculated using the peak slew rate from the equation
Peak Slew Rate
Full Power Bandwidth = 2π × Sinusoid Amplitude
The peak slew rate is not the same as the average slew rate. The
average slew rate is typically specified as the ratio
VOUT
t
measured between the 20% to 80% output levels of a suffi-
ciently large output pulse. For a natural response, the peak slew
rate may be 2.7 times larger than the average slew rate. There-
fore, calculating a full power bandwidth with a specified average
slew rate will give a pessimistic result. In specifying the large
signal performance of these multiplexers, we’ve published the
large-signal bandwidth, the average slew rate, and the measure-
ments of the total harmonic distortion. (Large signal bandwidth
is defined as the –3 dB point measured on a 2 V p-p output
sine wave.) Specifying these three aspects of the signal path’s
large signal dynamics allows the user to predict system behavior
for either pulse or sinusoid waveforms.
Single-Supply Considerations
DC-Coupled Inputs, Integrated Reference Buffers, and
Selecting the VREF Level on the AD8187, (G = +2)
The AD8186 and AD8187 offer superior large signal dynamics.
The trade-off is that the input and output compliance is limited
to ~1.3 V from either rail when driving a 150 load. These
sections address some challenges of designing video systems
within a single 5 V supply.
The AD8186
The AD8186 is internally wired as a unity-gain follower. Its
inputs and outputs can both swing to within ~1.3 V of either
rail. This affords the user 2.4 V of dynamic range at input and
output, which should be enough for most video signals, whether
the inputs are ac- or dc-coupled. In both cases, the choice of
output termination voltage will determine the quiescent load
current.
For improved supply rejection, the VREF pin should be tied to
an ac ground (the more quiet supply is a good bet). Internally,
the VREF pin connects to one terminal of an on-chip capacitor.
The capacitor’s other terminal connects to an internal node.
The consequence of building this bypass capacitor on-chip is
twofold. First, the VREF pin on the AD8186 draws no input bias
current. (Contrast this to the case of the AD8187, where the
VREF pin typically draws 2 µA of input bias current). Second,
on the AD8186, the VREF pin may be tied to any voltage within
the supply range.
IN0A
IN0B
IN1A
IN1B
IN2A
IN2B
VREF
AD8186
MUX SYSTEM
OUT0
OUT1
OUT2
“C_BYPASS”
INTERNAL CAP
BIAS REFERENCE
DIRECT CONNECTION TO ANY “QUIET” AC GROUND
(FOR EXAMPLE, GND, VCC, VEE)
Figure 3. VREF Pin Connection for AD8186 (Differs
from AD8187)
–12–
REV. A
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